Dr Bruce Griffiths said the following on 04/09/2007 09:20 AM:

Actually, there are BNC and TNC connectors available for LMR-400 -- even
crimp types!  I get most of my connectors from RF Industries, who have a
huge selection and pretty good prices.  But these were jumpers from the
8-port amplifier over to the racks where the GPS devices live, and a bit
more flexibility was desired.

John

Bruce,

the following is part of a discussion in comp.arch.fpga:

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.
Hi,
I would like to know what are the common methods of introducing
delays as low as 10ps between two outputs in an FPGA. I do not
currently have a specific FPGA in mind. I am just looking for a
general answer.

I know there are DCMs but this usually adds jitter and one needs to
wait for the DCM output to phase lock before the signal is stable and
it might take too long in our case. Basically I would want to power up
a board and have the delay be set in as short a time as possible. I
also need to minimise jitter to a minimum so that the two signals are
NEVER high at the same time. Thanks for any answer.
Amish
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Amish,
The only method I am aware of is hand routing.  10ps is too small to
really be able to hold to in all cases.  With 35ps p-p jitter (minimum)
in any FPGA, and +/- 10 ps route matching (due to process variations
chip to chip), this may be impossible.
Austin (Leesa)
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..
Austin,

I am currently designing some circuitry that needs to have jitter as low
as
possible, therefore this spec is most interesting for me. Are you
talking
about jitter introduced by DCMs or does ANY logic contained in an FPGA
exhibit this jitter even when clocked with a low jitter clock. I have a
0.8
ps RMS jitter clock source available (DS4077). If the logic that I would

like to clock with it would make a 35 ps pp minimum jitter out of it
this
would be a sheer catastrophe for me!
Best regards
Ulrich Bangert
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..
Ulrich,
Just go into any CMOS chip, and then immediately leave that chip.
That is 35 ps right there (a 74AHC04 for example).
If you use LVDS, and have perfect terminations, maybe it becomes 25 ps.
Call it a limitation of the technology of bulk CMOS.
If you do anything else, the number just gets bigger.
If you anything wrong, the number also gets bigger (bad bypassing, bad
SI, etc.)
Austin (Leesa)
........................................................................
..

Austin Leesa's opinion is in heavy contrast to your table but he is a
very experienced man. So, whom to believe?

Best regards
Ulrich Bangert

Ulrich Bangert wrote:

Ulrich

The table was snipped from an Analog Devices application note (AN501).
The ECL jitter is consistent with what I would expect.
However the CMOS jitter, particularly for HCMOS is about 10x less than I
would have expected.
Which is why I would like to find another technique to measure it.
If its around 25 ps RMS or more than it can probably be done with an HP5370.
It is just possible a decimal point was misplaced.
However we need to be certain everyone is using the same jitter measure
ie. RMS.
Also need to know what the measurement bandwidth is.
Austins figures seem OK for HCMOS but somewhat too high for ACMOS.

Since there are commercial CMOS output crystal oscillators with 25ps
jitter, the jitter of CMOS devices (at least at room temperature) can be
a little better than 35ps.

Also there a CMOS TDCs with a jitter considerably better than 10ps.

The jitter quoted is presumably for a very low jitter fast risetime source.
Thus the input noise of the gate has no effect on the output jitter
because the input signal slew rate is too high.
Only the intrinsic jitter of the gate is effective.

It would be nice to have a reliable set of figures for the jitter of
CMOS devices (ECL jitter is somewhat more difficult to measure).

In principle one could use a chain of inverters and use a time interval
counter or other technique to measure the statistics of the propagation
delay of a single gate near the end of the chain where the input slew
rate is as high as its going to be.

In principle its probably just possible to build a relatively
inexpensive analog (current source + capacitor plus schottky diodes and
an ADC) circuit that can actually measure sub picosecond jitter. It is
certainly very easy if its done on an SiGe chip, but the current limits
of discrete construction are a little uncertain. It may be possible with
8GHz transistor arrays.

I await Bob Paddock's circuit with bated breath.

Bruce

Enrico Rubiola wrote:

Enrico

Then we would need to know/measure the jitter of the retiming flipflop.
There appears to be little definitive published data on the jitter of
various logic gates and flipflops.
Consequently a simple reliable method of measuring such jitter would be
useful.

Bruce

Expected values
microwave: -120 dBrad^2/Hz flicker, -150 dB white
RF:                -140 dBrad^2/Hz flicker, -150 dB white
Use a double balanced mixer, traditional configuration.
A correlation scheme is probably not  necessary.

On the understanding side, aliasing is the beast to kill.
A logic gate shows a gain g<>0 (analog gain!!!) during the
edges, for it behaves as a sampling system -> increased
noise bandwidth, due to aliasing.

William Egan wrote an illuminating article, Transact. UFFC
(1990 in my notebooks, 1992 in my memory, sorry)

I know.  Fred L. Walls did some work, proc. Freq. Control Symp,
I don't remember when.

See above

Whoever has data, please send.

Cheers,

Enrico

Enrico Rubiola
professor of electronics

web: http://rubiola.org
e-mail: rubiola@femto-st.fr

FEMTO-ST Institute
32 av. de l'Observatoire
25044 Besancon, FRANCE
voice: +33(0)381.853940 (E.Rubiola)
voice: +33(0)381.853999 (switchboard)
fax: +33(0)381.853998

From: Enrico Rubiola rubiola@femto-st.fr
Subject: Re: [time-nuts] Gate propagation delay jitter
Date: Wed, 11 Apr 2007 00:14:01 +0200
Message-ID: AD07B1AE-765F-471B-A549-7F09F023EC91@femto-st.fr

Enrico,

So you mean I could toss in a double-balanced mixer and feed it with the
sampling clock and the output lines, while feeding the flip-flop some lower
clock?

It is a sampling system. It is just that it attempts to gain out the signal to
be either high or low.

Wouln't meta-stability be an issue here?

It is at times like this I am sad I don't have that access anymore. It was
too much money for me at the time.

Cheers,
Magnus

Magnus Danielson wrote:

Magnus

The traditional method is to use a pair of fliflops each dividing the
clock frequency by 2, one flipflop per mixer input.
Both inputs to the mixer should have the same frequency, so each
flipflop could be used to resynchronise a lower frequency data input.

Bruce

Found a copy of the circuit I had in mind on line, look at figure #25:

http://www.linear-tech.co.jp/pc/downloadDocument.do?navId=H0,C1,C1155,C1001,C1158,P1442,D1594

That circuit has a few problems, it is also based on ten year old parts.

One of the problems that is easy to fix is related to the bad divider thread.
In a multi-input gate, especially Schmitt Trigger ones, never connect
the inputs together.  There is the obvious problem of more capacitance
on the input, but there is the more subtle difference in switching time
of the inputs within the same gate adding.  Connect the unneeded inputs
to the appropriate logic levels.

Make a current source out of a current feed back op-amp that
has a high slew rate for charging the cap, feeding a fast track&hold.
The A/D itself does not have to be all that fast, as long as there
is little drupe before the sampling cap starts to discharge.

Also check out:

"High-Speed Time-Domain Measurements—Practical Tips for Improvement"

http://www.analog.com/library/analogDialogue/archives/41-03/time_domain.html

--
http://www.softwaresafety.net/ http://www.designer-iii.com/
http://www.unusualresearch.com/

6a

30-40 ps seems OK to me. But are you saying then that you
get a measured value to 200 fs resolution but with +/- 30 ps
standard deviation? This doesn't feel right at all. It seems to me
if your sdev is +/- 30 ps it is incorrect to even write down the
measured values to ps levels; and fs are out of the question.

/