Hi all,
I'm trying to build a GPSDO with a FVXO-HC53BR-10 (Fox Electronics) VCXO
and a Telit Jupiter
http://www.digikey.com/Suppliers/it/Fox-Electronics.page?lang=enSE880http://www.digikey.com/Suppliers/it/Fox-Electronics.page?lang=en,
this serves for a datalogger an I want to achieve a highly reliable clock.
This GPS receiver has two clock inputs: a 16MHz, and a 32KHz XT input
for the RTC functions.
My problem is this: The crystal must be driven by a voltage depending to
the phase difference between the GPS 1PPS output and the uC 1s cycles,
but must I drive (feedback) the RTC of the GPS also from a divider of
the main clock, or the 16MHz TCXO input, or both (or none...)?
Suggestions of any other component, for driving both the VCXO, and
possibly for a RTK implementation, are welcome.
Thank you,
Ilia.
On Mon, 25 Apr 2016 21:41:57 +0200
Ilia Platone info@iliaplatone.com wrote:
I'm trying to build a GPSDO with a FVXO-HC53BR-10 (Fox Electronics) VCXO
Please note that the HC53 family is what is commonly called "programmable
crystal oscillator". Which means it is a combination of a crystal oscillator
with a VCO and a PLL. The crystal runs at an arbitrary frequency and is
used to stabilize the VCO. The use of a standard crystal makes these devices
very cheap, but their phase noise performance is rather bad.
Quite interestingly, Fox has a quite extensive specification for
the jitter performance and splits it into random (aka noise) jitter
and deterministic (aka spurs) jitter. Curiously, there are no spurs
visible in the phase noise plot, which I find rather odd.
You might want to spend a couple of more bucks and get something
like the DOT050 from Connor Winfield that is a true crystal oscillator.
and a Telit Jupiter
http://www.digikey.com/Suppliers/it/Fox-Electronics.page?lang=enSE880http://www.digikey.com/Suppliers/it/Fox-Electronics.page?lang=en,
this serves for a datalogger an I want to achieve a highly reliable clock.
This GPS receiver has two clock inputs: a 16MHz, and a 32KHz XT input
for the RTC functions.
My problem is this: The crystal must be driven by a voltage depending to
the phase difference between the GPS 1PPS output and the uC 1s cycles,
It does not need to. The GPS module does not care about whether its
oscillator is exactly on frequency or not and what the phase of it is.
You can of course phase lock it to the PPS and to make it stable, but
you dont have to.
but must I drive (feedback) the RTC of the GPS also from a divider of
the main clock, or the 16MHz TCXO input, or both (or none...)?
The RTC is only there to give the GPS module a rough estimate of the
time so it can use the stored ephimeris data to speed up the search
for satellites. Ie there is no need to phase lock or stabilize the 32kHz
in any way.
Suggestions of any other component, for driving both the VCXO, and
possibly for a RTK implementation, are welcome.
For RTK you need satellite phase data. Most of the GPS modules do not
provide this information. I could not figure out whether the SE880 does
or does not provide it. There is quite a bit of lack of documentation
for that module, especially the communcation protocol (no, "NMEA standard"
does not mean anything).
Unless you already bought a SE880 already, i would recommend to
go with one of the u-blox modules (preferably the timing modules)
or get a LTE-Lite from Jackson Labs.
Attila Kinali
--
Reading can seriously damage your ignorance.
-- unknown
On Monday, April 25, 2016 09:41:57 PM Ilia Platone wrote:
Hi all,
I'm trying to build a GPSDO with a FVXO-HC53BR-10 (Fox Electronics) VCXO
and a Telit Jupiter
http://www.digikey.com/Suppliers/it/Fox-Electronics.page?lang=enSE880<http
://www.digikey.com/Suppliers/it/Fox-Electronics.page?lang=en>, this serves
for a datalogger an I want to achieve a highly reliable clock.
This GPS receiver has two clock inputs: a 16MHz, and a 32KHz XT input
for the RTC functions.
My problem is this: The crystal must be driven by a voltage depending to
the phase difference between the GPS 1PPS output and the uC 1s cycles,
but must I drive (feedback) the RTC of the GPS also from a divider of
the main clock, or the 16MHz TCXO input, or both (or none...)?
Suggestions of any other component, for driving both the VCXO, and
possibly for a RTK implementation, are welcome.
Thank you,
Ilia.
time-nuts mailing list -- time-nuts@febo.com
To unsubscribe, go to
https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the
instructions there.
What are the timing specifications for the data logging system?
Without this data, its not possible to decide if the proposed GPSDO will meet
these specifications.
Whist its possible to construct a GPSDO using almost any crystal controlled
oscillator, the timing performance will vary widely.
The datasheet for the Fox VCXO you selected does not specify the phasenoise,
jitter or ADEV for the 10MHZ option.
Bruce
On 4/25/16 1:36 PM, Attila Kinali wrote:
On Mon, 25 Apr 2016 21:41:57 +0200
Ilia Platone info@iliaplatone.com wrote:
I'm trying to build a GPSDO with a FVXO-HC53BR-10 (Fox Electronics) VCXO
Please note that the HC53 family is what is commonly called "programmable
crystal oscillator". Which means it is a combination of a crystal oscillator
with a VCO and a PLL. The crystal runs at an arbitrary frequency and is
used to stabilize the VCO. The use of a standard crystal makes these devices
very cheap, but their phase noise performance is rather bad.
No kidding.. we have one of those in a breadboard receiver and the phase
noise makes acquiring a narrow band BPSK modulated signal virtually
impossible. We use it to verify that the circuit design is ok (e.g. we
grab the right number of samples from the ADC in the right amount of
time), but trying to get carrier lock is a dicey proposition.
I haven't bought anything yet, so feel free to recommend me any
components/setup.
here is the datasheet I am referring to:
http://www.foxonline.com/pdfs/FVXO_HC53.pdf
It contains some informations about phase jitter on page 5.
The
I selected this because of the CMOS output, since I didn't find any
Connor Winfield osc with these levels yet.
Actually want to achieve less than around 78ps jitter at 125MHz. (this
should be achievable using this also:
http://www.digikey.it/product-detail/it/fox-electronics/FVXO-HC53B-125/FVXO-HC53B-125-ND/2153894)
Let me know,
Ilia.
Il 25/04/2016 22:51, Bruce Griffiths ha scritto:
On Monday, April 25, 2016 09:41:57 PM Ilia Platone wrote:
Hi all,
I'm trying to build a GPSDO with a FVXO-HC53BR-10 (Fox Electronics) VCXO
and a Telit Jupiter
http://www.digikey.com/Suppliers/it/Fox-Electronics.page?lang=enSE880<http
://www.digikey.com/Suppliers/it/Fox-Electronics.page?lang=en>, this serves
for a datalogger an I want to achieve a highly reliable clock.
This GPS receiver has two clock inputs: a 16MHz, and a 32KHz XT input
for the RTC functions.
My problem is this: The crystal must be driven by a voltage depending to
the phase difference between the GPS 1PPS output and the uC 1s cycles,
but must I drive (feedback) the RTC of the GPS also from a divider of
the main clock, or the 16MHz TCXO input, or both (or none...)?
Suggestions of any other component, for driving both the VCXO, and
possibly for a RTK implementation, are welcome.
Thank you,
Ilia.
time-nuts mailing list -- time-nuts@febo.com
To unsubscribe, go to
https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the
instructions there.
What are the timing specifications for the data logging system?
Without this data, its not possible to decide if the proposed GPSDO will meet
these specifications.
Whist its possible to construct a GPSDO using almost any crystal controlled
oscillator, the timing performance will vary widely.
The datasheet for the Fox VCXO you selected does not specify the phasenoise,
jitter or ADEV for the 10MHZ option.
Bruce
time-nuts mailing list -- time-nuts@febo.com
To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts
and follow the instructions there.
There's no spec for th 10MHz option you originally specified.What's the jitter bandwidth of interest?
Still need a spec for the data logging system timebase error.This is for your intensity interferometer?
Bruce
On Tuesday, 26 April 2016 10:00 AM, Ilia Platone <info@iliaplatone.com> wrote:
I haven't bought anything yet, so feel free to recommend me any
components/setup.
here is the datasheet I am referring to:
http://www.foxonline.com/pdfs/FVXO_HC53.pdf
It contains some informations about phase jitter on page 5.
The
I selected this because of the CMOS output, since I didn't find any
Connor Winfield osc with these levels yet.
Actually want to achieve less than around 78ps jitter at 125MHz. (this
should be achievable using this also:
http://www.digikey.it/product-detail/it/fox-electronics/FVXO-HC53B-125/FVXO-HC53B-125-ND/2153894)
Let me know,
Ilia.
Il 25/04/2016 22:51, Bruce Griffiths ha scritto:
On Monday, April 25, 2016 09:41:57 PM Ilia Platone wrote:
Hi all,
I'm trying to build a GPSDO with a FVXO-HC53BR-10 (Fox Electronics) VCXO
and a Telit Jupiter
http://www.digikey.com/Suppliers/it/Fox-Electronics.page?lang=enSE880<http
://www.digikey.com/Suppliers/it/Fox-Electronics.page?lang=en>, this serves
for a datalogger an I want to achieve a highly reliable clock.
This GPS receiver has two clock inputs: a 16MHz, and a 32KHz XT input
for the RTC functions.
My problem is this: The crystal must be driven by a voltage depending to
the phase difference between the GPS 1PPS output and the uC 1s cycles,
but must I drive (feedback) the RTC of the GPS also from a divider of
the main clock, or the 16MHz TCXO input, or both (or none...)?
Suggestions of any other component, for driving both the VCXO, and
possibly for a RTK implementation, are welcome.
Thank you,
Ilia.
time-nuts mailing list -- time-nuts@febo.com
To unsubscribe, go to
https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the
instructions there.
What are the timing specifications for the data logging system?
Without this data, its not possible to decide if the proposed GPSDO will meet
these specifications.
Whist its possible to construct a GPSDO using almost any crystal controlled
oscillator, the timing performance will vary widely.
The datasheet for the Fox VCXO you selected does not specify the phasenoise,
jitter or ADEV for the 10MHZ option.
Bruce
time-nuts mailing list -- time-nuts@febo.com
To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts
and follow the instructions there.
time-nuts mailing list -- time-nuts@febo.com
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and follow the instructions there.
On Mon, 25 Apr 2016 23:34:52 +0200
Ilia Platone info@iliaplatone.com wrote:
I selected this because of the CMOS output, since I didn't find any
Connor Winfield osc with these levels yet.
To get to CMOS levels, you usually add a simple inverter, with an
capacitor in front and a 1M resistor across the inverter (from input
to output).
Actually want to achieve less than around 78ps jitter at 125MHz. (this
should be achievable using this also:
http://www.digikey.it/product-detail/it/fox-electronics/FVXO-HC53B-125/FVXO-HC53B-125-ND/2153894)
I think you are mixing up a few things here:
Your logger might have very relaxed jitter requirements, but the
GPS module needs a low noise reference signal. If you feed it with
the noisy HC53 output, you will degrade your GPS receivers performance
severely. At the minimum, you should use a normal XO for the GPS modul.
You can of corse use a HC53 as the reference for your logger if its
jitter is ok for you.
And for comparison, for a XO you usually talk about jitter in the
order of 100fs to 1ps (10kHz-20MHz)
Attila Kinali
--
Reading can seriously damage your ignorance.
-- unknown
:) yes, it is.
Basically I need to sync two signals at a variable frequency centered at
about 10MHz, for 8 hours. The actual bandwidth depends because there
will be a variable number of harmonics on such signal.
The data logging system is for the intensity interferometer, and it
needs an error management like the above, it will use a PLL of an FPGA
that pulls up the frequency from the main oscillator into 400MHz, the
FPGA's PLL is very flexible, so the main XT frequency may not be
obligatory at 10MHz.
Regards,
Ilia.
Il 26/04/2016 00:12, Bruce Griffiths ha scritto:
There's no spec for th 10MHz option you originally specified.What's the jitter bandwidth of interest?
Still need a spec for the data logging system timebase error.This is for your intensity interferometer?
Bruce
On Tuesday, 26 April 2016 10:00 AM, Ilia Platone <info@iliaplatone.com> wrote:
I haven't bought anything yet, so feel free to recommend me any
components/setup.
here is the datasheet I am referring to:
http://www.foxonline.com/pdfs/FVXO_HC53.pdf
It contains some informations about phase jitter on page 5.
The
I selected this because of the CMOS output, since I didn't find any
Connor Winfield osc with these levels yet.
Actually want to achieve less than around 78ps jitter at 125MHz. (this
should be achievable using this also:
http://www.digikey.it/product-detail/it/fox-electronics/FVXO-HC53B-125/FVXO-HC53B-125-ND/2153894)
Let me know,
Ilia.
Il 25/04/2016 22:51, Bruce Griffiths ha scritto:
On Monday, April 25, 2016 09:41:57 PM Ilia Platone wrote:
Hi all,
I'm trying to build a GPSDO with a FVXO-HC53BR-10 (Fox Electronics) VCXO
and a Telit Jupiter
http://www.digikey.com/Suppliers/it/Fox-Electronics.page?lang=enSE880<http
://www.digikey.com/Suppliers/it/Fox-Electronics.page?lang=en>, this serves
for a datalogger an I want to achieve a highly reliable clock.
This GPS receiver has two clock inputs: a 16MHz, and a 32KHz XT input
for the RTC functions.
My problem is this: The crystal must be driven by a voltage depending to
the phase difference between the GPS 1PPS output and the uC 1s cycles,
but must I drive (feedback) the RTC of the GPS also from a divider of
the main clock, or the 16MHz TCXO input, or both (or none...)?
Suggestions of any other component, for driving both the VCXO, and
possibly for a RTK implementation, are welcome.
Thank you,
Ilia.
time-nuts mailing list -- time-nuts@febo.com
To unsubscribe, go to
https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the
instructions there.
What are the timing specifications for the data logging system?
Without this data, its not possible to decide if the proposed GPSDO will meet
these specifications.
Whist its possible to construct a GPSDO using almost any crystal controlled
oscillator, the timing performance will vary widely.
The datasheet for the Fox VCXO you selected does not specify the phasenoise,
jitter or ADEV for the 10MHZ option.
Bruce
time-nuts mailing list -- time-nuts@febo.com
To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts
and follow the instructions there.
time-nuts mailing list -- time-nuts@febo.com
To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts
and follow the instructions there.
time-nuts mailing list -- time-nuts@febo.com
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and follow the instructions there.
--
Ilia Platone
via Ferrara 54
47841
Cattolica (RN), Italy
Cell +39 349 1075999
Thank you Attila,
Just for informations, as I must build the board from scratch, does this
design is good to implement into the datalogger?
I mean, for the second RTK purpose, does this u-blox module satisfy my
requirements (link below)?
http://www.opendigitalradio.org/lea-m8f-gpsdo
Regards,
Ilia.
Il 26/04/2016 01:36, Attila Kinali ha scritto:
On Mon, 25 Apr 2016 23:34:52 +0200
Ilia Platone info@iliaplatone.com wrote:
I selected this because of the CMOS output, since I didn't find any
Connor Winfield osc with these levels yet.
To get to CMOS levels, you usually add a simple inverter, with an
capacitor in front and a 1M resistor across the inverter (from input
to output).
Actually want to achieve less than around 78ps jitter at 125MHz. (this
should be achievable using this also:
http://www.digikey.it/product-detail/it/fox-electronics/FVXO-HC53B-125/FVXO-HC53B-125-ND/2153894)
I think you are mixing up a few things here:
Your logger might have very relaxed jitter requirements, but the
GPS module needs a low noise reference signal. If you feed it with
the noisy HC53 output, you will degrade your GPS receivers performance
severely. At the minimum, you should use a normal XO for the GPS modul.
You can of corse use a HC53 as the reference for your logger if its
jitter is ok for you.
And for comparison, for a XO you usually talk about jitter in the
order of 100fs to 1ps (10kHz-20MHz)
Attila Kinali
--
Ilia Platone
via Ferrara 54
47841
Cattolica (RN), Italy
Cell +39 349 1075999
Hi
On Apr 25, 2016, at 7:36 PM, Attila Kinali attila@kinali.ch wrote:
On Mon, 25 Apr 2016 23:34:52 +0200
Ilia Platone info@iliaplatone.com wrote:
I selected this because of the CMOS output, since I didn't find any
Connor Winfield osc with these levels yet.
To get to CMOS levels, you usually add a simple inverter, with an
capacitor in front and a 1M resistor across the inverter (from input
to output).
If you set up a modern (74AC or faster) inverter with a resistor from input to
output, you are very likely to get it running as an oscillator all on it’s own. That
oscillation may or may not add to the desired output.
Stick with a two resistor bias on the input … it’s a lot safer.
Actually want to achieve less than around 78ps jitter at 125MHz. (this
should be achievable using this also:
http://www.digikey.it/product-detail/it/fox-electronics/FVXO-HC53B-125/FVXO-HC53B-125-ND/2153894)
I think you are mixing up a few things here:
Your logger might have very relaxed jitter requirements, but the
GPS module needs a low noise reference signal. If you feed it with
the noisy HC53 output, you will degrade your GPS receivers performance
severely. At the minimum, you should use a normal XO for the GPS modul.
You can of corse use a HC53 as the reference for your logger if its
jitter is ok for you.
And for comparison, for a XO you usually talk about jitter in the
order of 100fs to 1ps (10kHz-20MHz)
Attila Kinali
--
Reading can seriously damage your ignorance.
-- unknown
time-nuts mailing list -- time-nuts@febo.com
To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts
and follow the instructions there.
Bob