The contents of the latest issue of: International Journal of Embedded and Real-Time Communication Systems (IJERTCS) Official Publication of the Information Resources Management Association Volume 1, Issue 2, April-June 2010 Published: Quarterly in Print and Electronically ISSN: 1947-3176 EISSN: 1947-3184 Published by IGI Publishing, Hershey-New York, USA www.igi-global.com/ijertcs Editor-in-Chief: Seppo Virtanen, University of Turku, Finland GUEST EDITOR PREFACE Juha Plosila, University of Turku, Finland To read the preface, please consult this issue of IJERTCS in your library. PAPER ONE Schedulability Analysis for Real Time On-Chip Communication with Wormhole Switching Zheng Shi, University of York, UK Alan Burns, University of York, UK Leandro Indrusiak, University of York, UK In this paper, the authors discuss a real-time on-chip communication service with a priority-based wormhole switching policy. The authors present a novel off-line schedulability analysis approach, worst case network latency analysis. By evaluating diverse inter-relationships and service attributes among the traffic flows, this approach can predict the packet network latency for all practical situations. The simulation results provide evidence that communication latency calculated using the real time analysis approach is safe, closely matching the figures obtained from simulation. To obtain a copy of the entire article, click on the link below. http://www.igi-global.com/Bookstore/Article.aspx?TitleId=42983 PAPER TWO Modeling Communication in Multi–Processor Systems–on–Chip Using Modular Connectors Leonidas Tsiopoulos, Åbo Akademi University, Finland Kaisa Sere, Åbo Akademi University, Finland Juha Plosila, University of Turku, Finland Formal methods of concurrent programming can be used to develop and verify complex Multi–Processor Systems–On–Chip in order to ensure that these systems satisfy their functional and communication requirements. The authors use the Action Systems formalism and show how asynchronous communication of Multi–Processor Systems–on–Chip can be modeled using generic connectors composed out of simple channel components. The paper proposes a new approach to modeling generic and hierarchical connectors for handling the complexity of on–chip communication and data flow. The authors’ goal is to avoid overloaded bus–based architectures and give a distributed framework. A case study presents the authors’ modeling methodology. To obtain a copy of the entire article, click on the link below. http://www.igi-global.com/Bookstore/Article.aspx?TitleId=42984 PAPER THREE Towards Sustainable Development of Energy-Aware Systems Luigia Petre, Åbo Akademi University, Finland Kaisa Sere, Åbo Akademi University, Finland Smart devices have pervaded our society and encouraged lifestyles that depend on them. One of the fundamental requirements for a successful dependency is that the general public be aware of the energy limitations of these devices and to stay in control of energy consumption. In this paper, the authors propose a formal specification method that takes energy into account. They propose two development approaches that can use these specifications to develop energy-aware systems in a sustainable manner. To obtain a copy of the entire article, click on the link below. http://www.igi-global.com/Bookstore/Article.aspx?TitleId=42985 PAPER FOUR Service-Oriented Development of Fault Tolerant Communicating Systems: Refinement Approach Linas Laibinis, Åbo Akademi University, Finland Elena Troubitsyna, Åbo Akademi University, Finland Sari Leppänen, Nokia Research Center, Finland Telecommunication systems must have a high degree of availability, that is, a high probability of correct and timely provision of requested services. To achieve this, correctness of software for such systems should be ensured. Application of formal methods helps increase confidence in building correct software. However, to be used in practice, formal methods should be well integrated into existing development process. In this paper, the authors propose a formal model-driven approach to development of communicating systems. The authors formalize and extend the Lyra approach—a top-down service-oriented method for development of communicating systems. Lyra is based on transformation and decomposition of models expressed in UML2. The authors formalize Lyra in the B Method by proposing a set of formal specification and refinement patterns reflecting the essential models and transformations of the Lyra phases. Moreover, this paper extends Lyra to integrate reasoning about fault tolerance in the entire development flow. To obtain a copy of the entire article, click on the link below. http://www.igi-global.com/Bookstore/Article.aspx?TitleId=42986 PAPER FIVE Hierarchical Agent Monitored Parallel On-Chip System: A Novel Design Paradigm and its Formal Specification Liang Guang, University of Turku, Finland Juha Plosila, University of Turku, Finland Jouni Isoaho, University of Turku, Finland Hannu Tenhunen, University of Turku, Finland In this paper, the authors present a formal specification of a novel design paradigm, hierarchical agent monitored SoCs (HAMSOC). The paradigm motivates dynamic monitoring in a hierarchical and distributed manner, with adaptive agents embedded for local and global operations. Formal methods are of essential importance to the development of such a novel and complex platform. As the initial effort, functional specification is indispensable to the non-ambiguous system modeling before potential property verification. The formal specification defines the manner by which the system can be constructed with hierarchical components and the representation of run-time information in modeling entities and every type of the monitoring operations. The syntax follows the standard set theory with additional glossary and notations introduced to facilitate practical SoC design process. A case study of hierarchical monitoring for power management in NoC (Network-on-chip), written with the formal specification, is demonstrated. To obtain a copy of the entire article, click on the link below. http://www.igi-global.com/Bookstore/Article.aspx?TitleId=42987 ***************************************************** For full copies of the above articles, check for this issue of the International Journal of Embedded and Real-Time Communication Systems (IJERTCS) (IJERTCS) in your institution's library. This journal is also included in the IGI Global aggregated “InfoSci-Journals” database: www.infosci-journals.com. ***************************************************** CALL FOR PAPERS Mission of IJERTCS: The mission of the International Journal of Embedded and Real-Time Communication Systems (IJERTCS) is to disseminate recent advancements and innovations in this interdisciplinary research area for field researchers, practitioners, scientists, academicians, students, and IT professionals. IJERTCS focuses on overcoming challenges involved in the rapid development of embedded communication systems towards feature-rich multimedia computers. Coverage of IJERTCS: Asynchronous and synchronous circuit techniques Design methods Embedded networks (built-in networks in embedded communication devices) Emerging new topics Fault-tolerant hardware and software technologies Formal design and verification methods Hardware and software solutions for protocol processing Hardware and software solutions for real-time systems Hardware platforms and technologies Hardware/software co-design Modeling and verification methods On-chip communication in SoC and NoC OWA (open wireless architecture) Performance modeling Platform based design Real-time computing Reconfigurable systems Security issues and technologies Single-chip SDR (software defined radio) solutions Software design Testing techniques Interested authors should consult the journal's manuscript submission guidelines at www.igi-global.com/ijertcs All inquiries and submissions should be sent to: Editor-in-Chief: Seppo Virtanen at seppo.virtanen@utu.fi