Questions about TAC frontend, and some measurements
Hello, while waiting fot the final doom, or a new
job (tough times here) here is another update of
the work I'm doing, sorry for the looong mail,
hope I'm not boring the readers.
I have a question about a some measurements I
made, and I'd like an opinion about a frontend
schematic I designed.
First the question about the problem:
in this graph (bottom right) there is the time
interval between the PPS from the PA6H GPS
module and the 10MHz form the FE5680A,
uncrambled and corrected for linear drift.
The graph periodically makes big steps, and
this happens in the morning hours, in the
few captures I made so far the fact happens
around 6am-8am in the morning:
http://www.flickr.com/photos/14336723@N08/8294131424/
another previous capture with span enough to
include 2 mornings:
http://www.flickr.com/photos/14336723@N08/8294131660/
I will make more tests to check if the problem is in
the gps receiver or in the FE5680 or in the way I'm taking
measurements. This will take a while.
Maybe there is a simple explanation that I cannot see
since I'm a total newbie i this field.
Where should I search first for the problem?
How I'm taking the measurements:
the measurements are taken with the racal 1992
connected to the point OutD in the centre of the
frontend I'm building:
http://www.flickr.com/photos/14336723@N08/8293076065/
The OutD will spit out a short negative pulse,
the width of this pulse is the same (or very near)
than the phase time interval between the rising
edges of the pps and the 10MHz.
The counter logs the pulse width using a 100MHz
scope probe set to 10x, DC coupled.
The plots are made using this script I wrote for the task :
http://pastebin.com/XmKQp9gR
The (rude) script tries to unscramble the data, remove
outliers and correct for linear drift.
If it's useful I will upload the raw log data.
The frontend circuit:
As I wrote before I'm trying to feed a microcontroller
with 10MHz from a Rb oscillator and a PPS pulse from
a GPS module and see if I can obtain a good starting
point for building my own GPSDO.
Now I'm testing a front end that will present to the
micro both the PPS and 10MHz nicely squared, and
an analogue representation of the time interval between
the rising pulses of the sources.
What do you think of the circuit I designed?
(thanks to many resources coming from
this list, I passed much time on ko4bb site
and many others I dont even remember, thank you
all!) here the asc file for LTSpice:
http://pastebin.com/94H78jxs
I'm using components I had around or scavenged
in scrap electronics I had.
The TAC seem to work, but now I need a better
opamp (the LM358 has too much current
flowing in-out of the inputs), here a pair
of captures taken directly from C1 capacitor, 90nS pulse:
http://www.flickr.com/photos/14336723@N08/8293075961/
and a 50nS one:
http://www.flickr.com/photos/14336723@N08/8294131200/
The red trace is the input GPS PPS.
Fabio Eboli.
Hi
I think I would grab some sort of USB thermometer and start logging the room temperature.
CMOS input op-amps are a pretty good way to buffer the integrating capacitor. They are cheap and have very low bias currents.
Bob
On Dec 21, 2012, at 7:43 AM, FabioEb@quipo.it wrote:
Hello, while waiting fot the final doom, or a new
job (tough times here) here is another update of
the work I'm doing, sorry for the looong mail,
hope I'm not boring the readers.
I have a question about a some measurements I
made, and I'd like an opinion about a frontend
schematic I designed.
First the question about the problem:
in this graph (bottom right) there is the time
interval between the PPS from the PA6H GPS
module and the 10MHz form the FE5680A,
uncrambled and corrected for linear drift.
The graph periodically makes big steps, and
this happens in the morning hours, in the
few captures I made so far the fact happens
around 6am-8am in the morning:
http://www.flickr.com/photos/14336723@N08/8294131424/
another previous capture with span enough to
include 2 mornings:
http://www.flickr.com/photos/14336723@N08/8294131660/
I will make more tests to check if the problem is in
the gps receiver or in the FE5680 or in the way I'm taking
measurements. This will take a while.
Maybe there is a simple explanation that I cannot see
since I'm a total newbie i this field.
Where should I search first for the problem?
How I'm taking the measurements:
the measurements are taken with the racal 1992
connected to the point OutD in the centre of the
frontend I'm building:
http://www.flickr.com/photos/14336723@N08/8293076065/
The OutD will spit out a short negative pulse,
the width of this pulse is the same (or very near)
than the phase time interval between the rising
edges of the pps and the 10MHz.
The counter logs the pulse width using a 100MHz
scope probe set to 10x, DC coupled.
The plots are made using this script I wrote for the task :
http://pastebin.com/XmKQp9gR
The (rude) script tries to unscramble the data, remove
outliers and correct for linear drift.
If it's useful I will upload the raw log data.
The frontend circuit:
As I wrote before I'm trying to feed a microcontroller
with 10MHz from a Rb oscillator and a PPS pulse from
a GPS module and see if I can obtain a good starting
point for building my own GPSDO.
Now I'm testing a front end that will present to the
micro both the PPS and 10MHz nicely squared, and
an analogue representation of the time interval between
the rising pulses of the sources.
What do you think of the circuit I designed?
(thanks to many resources coming from
this list, I passed much time on ko4bb site
and many others I dont even remember, thank you
all!) here the asc file for LTSpice:
http://pastebin.com/94H78jxs
I'm using components I had around or scavenged
in scrap electronics I had.
The TAC seem to work, but now I need a better
opamp (the LM358 has too much current
flowing in-out of the inputs), here a pair
of captures taken directly from C1 capacitor, 90nS pulse:
http://www.flickr.com/photos/14336723@N08/8293075961/
and a 50nS one:
http://www.flickr.com/photos/14336723@N08/8294131200/
The red trace is the input GPS PPS.
Fabio Eboli.
time-nuts mailing list -- time-nuts@febo.com
To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts
and follow the instructions there.
Hi Fabio,
I am not crazy about your 10 MHz input circuit. You might want to consider
investigating John Miles input arrangement at the following web site:
I used it to drive an input to a divider chip without the output resistor or
capacitor.
Bill....WB6BNQ
FabioEb@quipo.it wrote:
Hello, while waiting fot the final doom, or a new
job (tough times here) here is another update of
the work I'm doing, sorry for the looong mail,
hope I'm not boring the readers.
I have a question about a some measurements I
made, and I'd like an opinion about a frontend
schematic I designed.
First the question about the problem:
in this graph (bottom right) there is the time
interval between the PPS from the PA6H GPS
module and the 10MHz form the FE5680A,
uncrambled and corrected for linear drift.
The graph periodically makes big steps, and
this happens in the morning hours, in the
few captures I made so far the fact happens
around 6am-8am in the morning:
http://www.flickr.com/photos/14336723@N08/8294131424/
another previous capture with span enough to
include 2 mornings:
http://www.flickr.com/photos/14336723@N08/8294131660/
I will make more tests to check if the problem is in
the gps receiver or in the FE5680 or in the way I'm taking
measurements. This will take a while.
Maybe there is a simple explanation that I cannot see
since I'm a total newbie i this field.
Where should I search first for the problem?
How I'm taking the measurements:
the measurements are taken with the racal 1992
connected to the point OutD in the centre of the
frontend I'm building:
http://www.flickr.com/photos/14336723@N08/8293076065/
The OutD will spit out a short negative pulse,
the width of this pulse is the same (or very near)
than the phase time interval between the rising
edges of the pps and the 10MHz.
The counter logs the pulse width using a 100MHz
scope probe set to 10x, DC coupled.
The plots are made using this script I wrote for the task :
http://pastebin.com/XmKQp9gR
The (rude) script tries to unscramble the data, remove
outliers and correct for linear drift.
If it's useful I will upload the raw log data.
The frontend circuit:
As I wrote before I'm trying to feed a microcontroller
with 10MHz from a Rb oscillator and a PPS pulse from
a GPS module and see if I can obtain a good starting
point for building my own GPSDO.
Now I'm testing a front end that will present to the
micro both the PPS and 10MHz nicely squared, and
an analogue representation of the time interval between
the rising pulses of the sources.
What do you think of the circuit I designed?
(thanks to many resources coming from
this list, I passed much time on ko4bb site
and many others I dont even remember, thank you
all!) here the asc file for LTSpice:
http://pastebin.com/94H78jxs
I'm using components I had around or scavenged
in scrap electronics I had.
The TAC seem to work, but now I need a better
opamp (the LM358 has too much current
flowing in-out of the inputs), here a pair
of captures taken directly from C1 capacitor, 90nS pulse:
http://www.flickr.com/photos/14336723@N08/8293075961/
and a 50nS one:
http://www.flickr.com/photos/14336723@N08/8294131200/
The red trace is the input GPS PPS.
Fabio Eboli.
time-nuts mailing list -- time-nuts@febo.com
To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts
and follow the instructions there.
Hi Fabio,
On 12/21/2012 01:43 PM, FabioEb@quipo.it wrote:
Hello, while waiting fot the final doom, or a new
job (tough times here) here is another update of
the work I'm doing, sorry for the looong mail,
hope I'm not boring the readers.
I have a question about a some measurements I
made, and I'd like an opinion about a frontend
schematic I designed.
First the question about the problem:
in this graph (bottom right) there is the time
interval between the PPS from the PA6H GPS
module and the 10MHz form the FE5680A,
uncrambled and corrected for linear drift.
The graph periodically makes big steps, and
this happens in the morning hours, in the
few captures I made so far the fact happens
around 6am-8am in the morning:
http://www.flickr.com/photos/14336723@N08/8294131424/
another previous capture with span enough to
include 2 mornings:
http://www.flickr.com/photos/14336723@N08/8294131660/
Like Bob said, start logging the temperature.
Since you have about 86400 s period on this behaviour, I expect that
heating up in the morning (sun or just habits of humans roughly aligned
with sun patterns) be the reason, so this would be temperature
dependent. Plotting supply voltage may be another reason.
I will make more tests to check if the problem is in
the gps receiver or in the FE5680 or in the way I'm taking
measurements. This will take a while.
Maybe there is a simple explanation that I cannot see
since I'm a total newbie i this field.
Where should I search first for the problem?
If you assume temperature sensitivity, you can apply temperature on
either of these parts to see what triggers the reaction.
Make sure that one part settles before pushing the other, so you know
what is the effect of what.
How I'm taking the measurements:
the measurements are taken with the racal 1992
connected to the point OutD in the centre of the
frontend I'm building:
http://www.flickr.com/photos/14336723@N08/8293076065/
The OutD will spit out a short negative pulse,
the width of this pulse is the same (or very near)
than the phase time interval between the rising
edges of the pps and the 10MHz.
The counter logs the pulse width using a 100MHz
scope probe set to 10x, DC coupled.
Do you really get 1-2 cycle long difference measures that way?
You risk a high non-linearity at the small difference side otherwise, as
it takes time to wake the transistors.
The plots are made using this script I wrote for the task :
http://pastebin.com/XmKQp9gR
The (rude) script tries to unscramble the data, remove
outliers and correct for linear drift.
If it's useful I will upload the raw log data.
The frontend circuit:
As I wrote before I'm trying to feed a microcontroller
with 10MHz from a Rb oscillator and a PPS pulse from
a GPS module and see if I can obtain a good starting
point for building my own GPSDO.
Now I'm testing a front end that will present to the
micro both the PPS and 10MHz nicely squared, and
an analogue representation of the time interval between
the rising pulses of the sources.
What do you think of the circuit I designed?
(thanks to many resources coming from
this list, I passed much time on ko4bb site
and many others I dont even remember, thank you
all!) here the asc file for LTSpice:
http://pastebin.com/94H78jxs
I'm using components I had around or scavenged
in scrap electronics I had.
The TAC seem to work, but now I need a better
opamp (the LM358 has too much current
flowing in-out of the inputs), here a pair
of captures taken directly from C1 capacitor, 90nS pulse:
http://www.flickr.com/photos/14336723@N08/8293075961/
and a 50nS one:
http://www.flickr.com/photos/14336723@N08/8294131200/
The red trace is the input GPS PPS.
As I commented, you might want 1-2 cycles to pass, so adding a second
DFF might be needed for that task.
Like that you try your interpolator wings!
I do recommend you to check out the Wenzel clock input stage, which is
being deployed in the TADD-2 divider. Squares up sine clocks nicely.
Cheers,
Magnus
I answer here to Bob Bill and Magnus.
Hi
I think I would grab some sort of USB thermometer and start logging
the room temperature.
CMOS input op-amps are a pretty good way to buffer the integrating
capacitor.
They are cheap and have very low bias currents.
Bob
The suspect is temperature, the first
thing I'm suspecting is the FE5680A temp coefficient.
I didnt grasp the "real numbers", so I tried estimating
the local drift, i.e. the drift value every 2k samples.
Here the results:
http://www.flickr.com/photos/14336723@N08/8296002061/
The drift stays around -3.2x10^-10 then
abruptly goes to -2.4x10^-10, so if the culprit
is the 5680, it's frequency should change about 1x10^-10,
if I didnt screw up all the calculations.
Does this make sense?
As for the buffer opamp, I will try with MCP6001,
cheap and it's input impedance is so high I will be
limited by the pcb...
By the way, my LM358 seem to be injecting 1.5nA
into the ramp capacitor until it levels to around 1-1.5V.
Like Bob said, start logging the temperature.
Since you have about 86400 s period on this behaviour, I expect that
heating up in the morning (sun or just habits of humans roughly
aligned with sun patterns) be the reason, so this would be
temperature
dependent. Plotting supply voltage may be another reason.
Magnus, I will log some temperatures and voltages.
scope probe set to 10x, DC coupled.
Do you really get 1-2 cycle long difference measures that way?
You risk a high non-linearity at the small difference side otherwise,
as it takes time to wake the transistors.
...
As I commented, you might want 1-2 cycles to pass, so adding a second
DFF might be needed for that task.
So if I'm understanding you are suggesting to measure on the
second 10MHz edge, instead of the first, I would have 100 to 200nS
instead of 0 to 100nS. I didnt think about this, I like the idea!
Like that you try your interpolator wings!
Sorry, I didnt undestand this part.
I do recommend you to check out the Wenzel clock input stage, which
is being deployed in the TADD-2 divider. Squares up sine clocks
nicely.
Cheers,
Magnus
Hi Fabio,
I am not crazy about your 10 MHz input circuit. You might want to
consider
investigating John Miles input arrangement at the following web site:
http://www.ke5fx.com/ac.htm
I used it to drive an input to a divider chip without the output
resistor or
capacitor.
Bill....WB6BNQ
Magnus and Bill, the input stage I'm using was inspired by
the wenzel second schematic on this page:
http://www.wenzel.com/documents/waveform.html
But you both are right, I'm starting to see that it's
not that stable.
I will try the discrete solution on the wenzel page.
Is the transformer mandatory or I can avoid it?
In case I have some IF-cans but I've never used and
dont know much about them.
Thank you all,
Fabio.
Hi
It is often harder to measure a pulse that goes from 0 to 100 ns than it is to measure one that goes from 100 to 200 ns.
The resolution on the 0 to 100 measure will be 2X, but the non-linearities at zero are quite difficult to deal with. The 100 to 200 measure can get to the same resolution with some analog tricks. If you are running into an ADC, the resolution may already be "good enough". There may be no benefit from making it 2X better.
For the measurement you are trying to do, 0.1 ns is probably good enough. A 10 bit ADC would do that at 100 ns span. A 12 bit ADC would do it at a 200 ns span.
Bob
On Dec 22, 2012, at 8:34 AM, FabioEb@quipo.it wrote:
I answer here to Bob Bill and Magnus.
Hi
I think I would grab some sort of USB thermometer and start logging the room temperature.
CMOS input op-amps are a pretty good way to buffer the integrating capacitor.
They are cheap and have very low bias currents.
Bob
The suspect is temperature, the first
thing I'm suspecting is the FE5680A temp coefficient.
I didnt grasp the "real numbers", so I tried estimating
the local drift, i.e. the drift value every 2k samples.
Here the results:
http://www.flickr.com/photos/14336723@N08/8296002061/
The drift stays around -3.2x10^-10 then
abruptly goes to -2.4x10^-10, so if the culprit
is the 5680, it's frequency should change about 1x10^-10,
if I didnt screw up all the calculations.
Does this make sense?
As for the buffer opamp, I will try with MCP6001,
cheap and it's input impedance is so high I will be
limited by the pcb...
By the way, my LM358 seem to be injecting 1.5nA
into the ramp capacitor until it levels to around 1-1.5V.
Like Bob said, start logging the temperature.
Since you have about 86400 s period on this behaviour, I expect that
heating up in the morning (sun or just habits of humans roughly
aligned with sun patterns) be the reason, so this would be temperature
dependent. Plotting supply voltage may be another reason.
Magnus, I will log some temperatures and voltages.
scope probe set to 10x, DC coupled.
Do you really get 1-2 cycle long difference measures that way?
You risk a high non-linearity at the small difference side otherwise,
as it takes time to wake the transistors.
...
As I commented, you might want 1-2 cycles to pass, so adding a second
DFF might be needed for that task.
So if I'm understanding you are suggesting to measure on the
second 10MHz edge, instead of the first, I would have 100 to 200nS
instead of 0 to 100nS. I didnt think about this, I like the idea!
Like that you try your interpolator wings!
Sorry, I didnt undestand this part.
I do recommend you to check out the Wenzel clock input stage, which
is being deployed in the TADD-2 divider. Squares up sine clocks
nicely.
Cheers,
Magnus
Hi Fabio,
I am not crazy about your 10 MHz input circuit. You might want to consider
investigating John Miles input arrangement at the following web site:
http://www.ke5fx.com/ac.htm
I used it to drive an input to a divider chip without the output resistor or
capacitor.
Bill....WB6BNQ
Magnus and Bill, the input stage I'm using was inspired by
the wenzel second schematic on this page:
http://www.wenzel.com/documents/waveform.html
But you both are right, I'm starting to see that it's
not that stable.
I will try the discrete solution on the wenzel page.
Is the transformer mandatory or I can avoid it?
In case I have some IF-cans but I've never used and
dont know much about them.
Thank you all,
Fabio.
time-nuts mailing list -- time-nuts@febo.com
To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts
and follow the instructions there.
Dear Fabio,
On 12/22/2012 02:34 PM, FabioEb@quipo.it wrote:
I answer here to Bob Bill and Magnus.
Hi
I think I would grab some sort of USB thermometer and start logging
the room temperature.
CMOS input op-amps are a pretty good way to buffer the integrating
capacitor.
They are cheap and have very low bias currents.
Bob
The suspect is temperature, the first
thing I'm suspecting is the FE5680A temp coefficient.
When it comes to phase, your interpolator may also be sensitive.
I didnt grasp the "real numbers", so I tried estimating
the local drift, i.e. the drift value every 2k samples.
Here the results:
http://www.flickr.com/photos/14336723@N08/8296002061/
The drift stays around -3.2x10^-10 then
abruptly goes to -2.4x10^-10, so if the culprit
is the 5680, it's frequency should change about 1x10^-10,
if I didnt screw up all the calculations.
Does this make sense?
Sounds a bit on the high side.
As for the buffer opamp, I will try with MCP6001,
cheap and it's input impedance is so high I will be
limited by the pcb...
By the way, my LM358 seem to be injecting 1.5nA
into the ramp capacitor until it levels to around 1-1.5V.
Like Bob said, start logging the temperature.
Since you have about 86400 s period on this behaviour, I expect that
heating up in the morning (sun or just habits of humans roughly
aligned with sun patterns) be the reason, so this would be temperature
dependent. Plotting supply voltage may be another reason.
Magnus, I will log some temperatures and voltages.
Goodie.
scope probe set to 10x, DC coupled.
Do you really get 1-2 cycle long difference measures that way?
You risk a high non-linearity at the small difference side otherwise,
as it takes time to wake the transistors.
...
As I commented, you might want 1-2 cycles to pass, so adding a second
DFF might be needed for that task.
So if I'm understanding you are suggesting to measure on the
second 10MHz edge, instead of the first, I would have 100 to 200nS
instead of 0 to 100nS. I didnt think about this, I like the idea!
Indeed. Some even let one more edge go and measure between 200 and 300 ns.
Like that you try your interpolator wings!
Sorry, I didnt undestand this part.
Trivial, I like that you experiment and build your own interpolator
design, build experience.
I do recommend you to check out the Wenzel clock input stage, which
is being deployed in the TADD-2 divider. Squares up sine clocks
nicely.
Cheers,
Magnus
Hi Fabio,
I am not crazy about your 10 MHz input circuit. You might want to
consider
investigating John Miles input arrangement at the following web site:
http://www.ke5fx.com/ac.htm
I used it to drive an input to a divider chip without the output
resistor or
capacitor.
Bill....WB6BNQ
Magnus and Bill, the input stage I'm using was inspired by
the wenzel second schematic on this page:
http://www.wenzel.com/documents/waveform.html
But you both are right, I'm starting to see that it's
not that stable.
I will try the discrete solution on the wenzel page.
Good. It amplifies up the clock so that you will have low jitter.
Is the transformer mandatory or I can avoid it?
You can avoid it, just make sure that you get the transistors properly
biased, so DC blocking cap and some resistors.
In case I have some IF-cans but I've never used and
dont know much about them.
It's relative benign transistors being used.
Good luck and look forward to your progress reports.
You got me inspired to try something myself. :)
Cheers,
Magnus
Magnus Danielson wrote:
Dear Fabio,
On 12/22/2012 02:34 PM, FabioEb@quipo.it wrote:
I answer here to Bob Bill and Magnus.
Hi
I think I would grab some sort of USB thermometer and start logging
the room temperature.
CMOS input op-amps are a pretty good way to buffer the integrating
capacitor.
They are cheap and have very low bias currents.
Bob
The suspect is temperature, the first
thing I'm suspecting is the FE5680A temp coefficient.
When it comes to phase, your interpolator may also be sensitive.
I didnt grasp the "real numbers", so I tried estimating
the local drift, i.e. the drift value every 2k samples.
Here the results:
http://www.flickr.com/photos/14336723@N08/8296002061/
The drift stays around -3.2x10^-10 then
abruptly goes to -2.4x10^-10, so if the culprit
is the 5680, it's frequency should change about 1x10^-10,
if I didnt screw up all the calculations.
Does this make sense?
Sounds a bit on the high side.
As for the buffer opamp, I will try with MCP6001,
cheap and it's input impedance is so high I will be
limited by the pcb...
By the way, my LM358 seem to be injecting 1.5nA
into the ramp capacitor until it levels to around 1-1.5V.
Like Bob said, start logging the temperature.
Since you have about 86400 s period on this behaviour, I expect that
heating up in the morning (sun or just habits of humans roughly
aligned with sun patterns) be the reason, so this would be temperature
dependent. Plotting supply voltage may be another reason.
Magnus, I will log some temperatures and voltages.
Goodie.
scope probe set to 10x, DC coupled.
Do you really get 1-2 cycle long difference measures that way?
You risk a high non-linearity at the small difference side otherwise,
as it takes time to wake the transistors.
...
As I commented, you might want 1-2 cycles to pass, so adding a second
DFF might be needed for that task.
So if I'm understanding you are suggesting to measure on the
second 10MHz edge, instead of the first, I would have 100 to 200nS
instead of 0 to 100nS. I didnt think about this, I like the idea!
Indeed. Some even let one more edge go and measure between 200 and 300
ns.
Like that you try your interpolator wings!
Sorry, I didnt undestand this part.
Trivial, I like that you experiment and build your own interpolator
design, build experience.
I do recommend you to check out the Wenzel clock input stage, which
is being deployed in the TADD-2 divider. Squares up sine clocks
nicely.
Cheers,
Magnus
Hi Fabio,
I am not crazy about your 10 MHz input circuit. You might want to
consider
investigating John Miles input arrangement at the following web site:
http://www.ke5fx.com/ac.htm
I used it to drive an input to a divider chip without the output
resistor or
capacitor.
Bill....WB6BNQ
Magnus and Bill, the input stage I'm using was inspired by
the wenzel second schematic on this page:
http://www.wenzel.com/documents/waveform.html
But you both are right, I'm starting to see that it's
not that stable.
I will try the discrete solution on the wenzel page.
Good. It amplifies up the clock so that you will have low jitter.
Is the transformer mandatory or I can avoid it?
You can avoid it, just make sure that you get the transistors properly
biased, so DC blocking cap and some resistors.
In case I have some IF-cans but I've never used and
dont know much about them.
It's relative benign transistors being used.
Good luck and look forward to your progress reports.
You got me inspired to try something myself. :)
Cheers,
Magnus
Using saturated transistors as switches in the current source and
elsewhere isn't conducive to fast switching.
The traditional arrangement using current mode switches is much faster
and more predictable.
Buffering the ramp with an opamp requires that the opamp settling time
be known so that the opamp has fully settled before a sample is taken.
With a charge redistribution ADC that has a sampling switch connected to
a capacitor array a buffer isnt usually necessary.
Bruce
Bruce
When it comes to phase, your interpolator may also be sensitive.
Dont know if I was clear enough, just in case I wasnt able
to explain well before: the data I collected didnt came from
the analog interpolator, but from the OutD that is a digital
out. The interpolator is still in it's infancy.
So if I'm understanding you are suggesting to measure on the
second 10MHz edge, instead of the first, I would have 100 to 200nS
instead of 0 to 100nS. I didnt think about this, I like the idea!
Indeed. Some even let one more edge go and measure between 200 and
300 ns.
I modified the schematic this way to use the second edge:
http://www.flickr.com/photos/14336723@N08/8297438155/
Like that you try your interpolator wings!
Sorry, I didnt undestand this part.
Trivial, I like that you experiment and build your own interpolator
design, build experience.
Thanks, I like to experiment directly when I can.
This puts me in front of the real problems.
And by the way playing with the interpolator is
something that I'm enjoing; that few transistors
are making something that was sort of magic for me before:
converting nanoseconds pulses in something that can be easily
read. In this work I'm only starting and I'm already on the
edge of my little knowledge on electronics, and I'm learning
much from the resources and contributors to this list.
Good luck and look forward to your progress reports.
I will happily keep sharing the work.
You got me inspired to try something myself. :)
Wow :)
Thank you,
Fabio.
Hello, Bruce
Using saturated transistors as switches in the current source and
elsewhere isn't conducive to fast switching.
The traditional arrangement using current mode switches is much
faster and more predictable.
This is something I'd like to understand better.
I'm referring to this schematic here:
http://www.flickr.com/photos/14336723@N08/8293076065/
Q2 and Q5 are saturating toward the end of the
ramp pulse, when the ramp capacitor C1 starts
to go up.
I was prepared to see the circuit I designed
fail miserably on switch time, but it seem
to be working, as far as I could see on the DSO.
As far I can understand, the fact that Q2 and Q6
don't saturate, saves the circuit, since
at the end of the ramp, when Q1 and Q5 are
into saturation, Q6 is able to steer the
current to ground, and reverse bias BE (and CB)
of Q5. Is this correct, or I was only
lucky with the specific parts I used?
Buffering the ramp with an opamp requires that the opamp settling
time be known so that the opamp has fully settled before a sample is
taken. With a charge redistribution ADC that has a sampling switch
connected to a capacitor array a buffer isnt usually necessary.
Bruce
I was planning to read the voltage with a microcontroller's ADC.
I will set a fixed delay from the PPS rising edge and start
sampling there. To do so I need that the voltage on integrating
capacitor to stay reasonably stable during the delay.
Fabio