Questions about TAC frontend, and some measurements
Hi Fabio taking BJTs deep into saturation stores a lot of charge in the
collector base capacitance. this must br discharged before a state change
can occur. LSTTL gets round this and gets the speed at lower currents by
clamping the collector to only just in saturation with a schottky diode
between base and collector. Higher speeds are obtained with a long-tail pair
like configuration, which switches (diverts) the current flow between left
and right transistors for the two logic states. The current and power
dissipation is high but speeds 10 times saturated logic are obtainable. see
ECL, MECL, or PECL logic family schematics.
Alan
G3NYK
----- Original Message -----
From: "Fabio Eboli" FabioEb@quipo.it
To: "Discussion of precise time and frequency measurement"
time-nuts@febo.com
Sent: Saturday, December 22, 2012 11:00 PM
Subject: Re: [time-nuts] Questions about TAC frontend, and some measurements
Hello, Bruce
Using saturated transistors as switches in the current source and
elsewhere isn't conducive to fast switching.
The traditional arrangement using current mode switches is much
faster and more predictable.
This is something I'd like to understand better.
I'm referring to this schematic here:
http://www.flickr.com/photos/14336723@N08/8293076065/
Q2 and Q5 are saturating toward the end of the
ramp pulse, when the ramp capacitor C1 starts
to go up.
I was prepared to see the circuit I designed
fail miserably on switch time, but it seem
to be working, as far as I could see on the DSO.
As far I can understand, the fact that Q2 and Q6
don't saturate, saves the circuit, since
at the end of the ramp, when Q1 and Q5 are
into saturation, Q6 is able to steer the
current to ground, and reverse bias BE (and CB)
of Q5. Is this correct, or I was only
lucky with the specific parts I used?
Buffering the ramp with an opamp requires that the opamp settling
time be known so that the opamp has fully settled before a sample is
taken. With a charge redistribution ADC that has a sampling switch
connected to a capacitor array a buffer isnt usually necessary.
Bruce
I was planning to read the voltage with a microcontroller's ADC.
I will set a fixed delay from the PPS rising edge and start
sampling there. To do so I need that the voltage on integrating
capacitor to stay reasonably stable during the delay.
Fabio
time-nuts mailing list -- time-nuts@febo.com
To unsubscribe, go to
https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts
and follow the instructions there.
Google "baker clamp" for more on this.
Tom
----- Original Message -----
From: "Alan Melia" alan.melia@btinternet.com
To: "Discussion of precise time and frequency measurement"
time-nuts@febo.com
Sent: Saturday, December 22, 2012 6:28 PM
Subject: Re: [time-nuts] Questions about TAC frontend, and some measurements
Hi Fabio taking BJTs deep into saturation stores a lot of charge in the
collector base capacitance. this must br discharged before a state change
can occur. LSTTL gets round this and gets the speed at lower currents by
clamping the collector to only just in saturation with a schottky diode
between base and collector. Higher speeds are obtained with a long-tail pair
like configuration, which switches (diverts) the current flow between left
and right transistors for the two logic states. The current and power
dissipation is high but speeds 10 times saturated logic are obtainable. see
ECL, MECL, or PECL logic family schematics.
Alan
G3NYK
----- Original Message -----
From: "Fabio Eboli" FabioEb@quipo.it
To: "Discussion of precise time and frequency measurement"
time-nuts@febo.com
Sent: Saturday, December 22, 2012 11:00 PM
Subject: Re: [time-nuts] Questions about TAC frontend, and some measurements
Hello, Bruce
Using saturated transistors as switches in the current source and
elsewhere isn't conducive to fast switching.
The traditional arrangement using current mode switches is much
faster and more predictable.
This is something I'd like to understand better.
I'm referring to this schematic here:
http://www.flickr.com/photos/14336723@N08/8293076065/
Q2 and Q5 are saturating toward the end of the
ramp pulse, when the ramp capacitor C1 starts
to go up.
I was prepared to see the circuit I designed
fail miserably on switch time, but it seem
to be working, as far as I could see on the DSO.
As far I can understand, the fact that Q2 and Q6
don't saturate, saves the circuit, since
at the end of the ramp, when Q1 and Q5 are
into saturation, Q6 is able to steer the
current to ground, and reverse bias BE (and CB)
of Q5. Is this correct, or I was only
lucky with the specific parts I used?
Buffering the ramp with an opamp requires that the opamp settling
time be known so that the opamp has fully settled before a sample is
taken. With a charge redistribution ADC that has a sampling switch
connected to a capacitor array a buffer isnt usually necessary.
Bruce
I was planning to read the voltage with a microcontroller's ADC.
I will set a fixed delay from the PPS rising edge and start
sampling there. To do so I need that the voltage on integrating
capacitor to stay reasonably stable during the delay.
Fabio
time-nuts mailing list -- time-nuts@febo.com
To unsubscribe, go to
https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts
and follow the instructions there.
time-nuts mailing list -- time-nuts@febo.com
To unsubscribe, go to
https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts
and follow the instructions there.
Hi
One very simple question - how good would it do if you just did it all with logic gates? Tri-state buffers and things like that….
Now that you are up to a 100 to 200 ns long pulse, a lot of the fiddly stuff about "can't get a 2 ns pulse through it" goes away.
I'm not suggesting you tear up what you have. It's just something else to try and compare.
Bob
On Dec 22, 2012, at 6:00 PM, Fabio Eboli fabioeb@quipo.it wrote:
Hello, Bruce
Using saturated transistors as switches in the current source and
elsewhere isn't conducive to fast switching.
The traditional arrangement using current mode switches is much
faster and more predictable.
This is something I'd like to understand better.
I'm referring to this schematic here:
http://www.flickr.com/photos/14336723@N08/8293076065/
Q2 and Q5 are saturating toward the end of the
ramp pulse, when the ramp capacitor C1 starts
to go up.
I was prepared to see the circuit I designed
fail miserably on switch time, but it seem
to be working, as far as I could see on the DSO.
As far I can understand, the fact that Q2 and Q6
don't saturate, saves the circuit, since
at the end of the ramp, when Q1 and Q5 are
into saturation, Q6 is able to steer the
current to ground, and reverse bias BE (and CB)
of Q5. Is this correct, or I was only
lucky with the specific parts I used?
Buffering the ramp with an opamp requires that the opamp settling
time be known so that the opamp has fully settled before a sample is
taken. With a charge redistribution ADC that has a sampling switch
connected to a capacitor array a buffer isnt usually necessary.
Bruce
I was planning to read the voltage with a microcontroller's ADC.
I will set a fixed delay from the PPS rising edge and start
sampling there. To do so I need that the voltage on integrating
capacitor to stay reasonably stable during the delay.
Fabio
time-nuts mailing list -- time-nuts@febo.com
To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts
and follow the instructions there.
Fabio Eboli wrote:
Hello, Bruce
Using saturated transistors as switches in the current source and
elsewhere isn't conducive to fast switching.
The traditional arrangement using current mode switches is much
faster and more predictable.
This is something I'd like to understand better.
I'm referring to this schematic here:
http://www.flickr.com/photos/14336723@N08/8293076065/
Q2 and Q5 are saturating toward the end of the
ramp pulse, when the ramp capacitor C1 starts
to go up.
I was prepared to see the circuit I designed
fail miserably on switch time, but it seem
to be working, as far as I could see on the DSO.
As far I can understand, the fact that Q2 and Q6
don't saturate, saves the circuit, since
at the end of the ramp, when Q1 and Q5 are
into saturation, Q6 is able to steer the
current to ground, and reverse bias BE (and CB)
of Q5. Is this correct, or I was only
lucky with the specific parts I used?
Buffering the ramp with an opamp requires that the opamp settling
time be known so that the opamp has fully settled before a sample is
taken. With a charge redistribution ADC that has a sampling switch
connected to a capacitor array a buffer isnt usually necessary.
Bruce
I was planning to read the voltage with a microcontroller's ADC.
I will set a fixed delay from the PPS rising edge and start
sampling there. To do so I need that the voltage on integrating
capacitor to stay reasonably stable during the delay.
Fabio
The classic TAC using current mode switching is similar to the attached
circuit schematic.
The reset circuit uses a pair of matched diodes with nominally equal
currents flowing in them to ensure a controlled reset with low offset.
The enhanced current sources improve the current source output impedance
over that of a simple current source.
Opamps can be used to improve the current source accuracy however
maintaining the current source output impedance at high frequencies can
then be problematic if suitable decoupling of the opamp from the current
source emitter and base isnt used.
Only the sampling jitter is significant in that combined with the
leakage current in hold mode it is equivalent to a much smaller timing
jitter at the input.
For example a 1uA leakage current in hold mode combined with a 10mA
charging current is equivalent to 100ps of TAC input jitter.
Using faster lower capacitance transistors is helpful in reducing
nonlinearities.
Bruce
Fabio Eboli wrote:
Hello, Bruce
Using saturated transistors as switches in the current source and
elsewhere isn't conducive to fast switching.
The traditional arrangement using current mode switches is much
faster and more predictable.
This is something I'd like to understand better.
I'm referring to this schematic here:
http://www.flickr.com/photos/14336723@N08/8293076065/
Q2 and Q5 are saturating toward the end of the
ramp pulse, when the ramp capacitor C1 starts
to go up.
I was prepared to see the circuit I designed
fail miserably on switch time, but it seem
to be working, as far as I could see on the DSO.
As far I can understand, the fact that Q2 and Q6
don't saturate, saves the circuit, since
at the end of the ramp, when Q1 and Q5 are
into saturation, Q6 is able to steer the
current to ground, and reverse bias BE (and CB)
of Q5. Is this correct, or I was only
lucky with the specific parts I used?
The simulation indicates that the TAC capacitor charging current is far
from constant whilst charging.
This is due to the use of saturated switches rather than current
steering switches.
The capacitor charging current is poorly controlled.
So in this respect your circuit fails miserably.
bruce
Il 2012-12-23 11:36 Bruce Griffiths ha scritto:
The simulation indicates that the TAC capacitor charging current is
far from constant whilst charging.
This is due to the use of saturated switches rather than current
steering switches.
The capacitor charging current is poorly controlled.
So in this respect your circuit fails miserably.
So if I'm understanding correctly, the non linearity is due
to the uncontrolled current flowing from the collectors to
the bases of saturated transistors, that changes the magnitude
of charging current in uncontrolled way.
I was trying to use a sungle supply, but now I'm starting to
see the limits of my implementations.
Fabio.
Il 2012-12-23 07:42 Bruce Griffiths ha scritto:
The classic TAC using current mode switching is similar to the
attached circuit schematic.
Bruce I tried to replicate the circuit
you attached, the pic was low resolution
so I tried to figure the values.
This is the circuit asc text
http://pastebin.com/EkgqmgfE
If you have time please check it,
and tell me the errors, thanks.
I wish to all the members of the list a happy Christmas
Fabio.
Fabio Eboli wrote:
Il 2012-12-23 07:42 Bruce Griffiths ha scritto:
The classic TAC using current mode switching is similar to the
attached circuit schematic.
Bruce I tried to replicate the circuit
you attached, the pic was low resolution
so I tried to figure the values.
This is the circuit asc text
http://pastebin.com/EkgqmgfE
If you have time please check it,
and tell me the errors, thanks.
I wish to all the members of the list a happy Christmas
Fabio.
Fabio
The capacitance of the BAT46 diodes is too large to be particularly useful.
HSMS282x series diodes from Avago are a better choice.
I can send you a Spice model for these if you want.
This model can easily be added to the LTSpice diode collection.
Bruce
Fabio Eboli wrote:
Il 2012-12-23 11:36 Bruce Griffiths ha scritto:
The simulation indicates that the TAC capacitor charging current is
far from constant whilst charging.
This is due to the use of saturated switches rather than current
steering switches.
The capacitor charging current is poorly controlled.
So in this respect your circuit fails miserably.
So if I'm understanding correctly, the non linearity is due
to the uncontrolled current flowing from the collectors to
the bases of saturated transistors, that changes the magnitude
of charging current in uncontrolled way.
I was trying to use a sungle supply, but now I'm starting to
see the limits of my implementations.
Fabio.
Corrections:
R6 = 250 ohm
R14 = 125 ohm
R10 = 250 ohm
R5 = 250 ohm
R2 = 2k ohm
The current source tempco is around 2000ppm/C
This can be reduced to about 100ppm/C (limited by hfe tempco of the
transistors) by replacing the LEDS with emitter followers the base of
which is driven by an opamp.
Bruce
Fabio
The simplest (lowest part count and least number of power supplies)
consists of a tristate buffer driving an RC circuit.
The PPS signal is connected directly to the buffer input whilst the
output of the PPS synchroniser (at least 2 stages to minimise the
probability of metastabilty at the synchroniser output) drives the
buffer tristate control input.
The RC network starts charging when the PPS signal goes high and stops
when the synchroniser output goes high.
The capacitor charging is nonlinear but this is easily corrected in
software.
The capacitor is connected between the input of a capacitive charge
redistribution ADC and ground.
Software correction for the effect of charging the charge ADC input
capacitance is also required.
Suitable fast single gate tristate drives are readily available.
With low tempco resistors and capacitors the TAC gain tempco can be
200pmm/C or less.
The only disadvantages are the increased software complexity and the
need for an extra bit of ADC resolution to maintain TAC resolution.
Bruce