Gilbert cells are very useful in many "compromise" circuits. If you have a
fixed power budget on the very low end, Gilbert cells may be the best
choice because they make a balanced mixer stage that has substantial gain
with miniscule LO drive requirements.
Contrast that with a DBM diode mixer where they take substantial LO drive
and operate some loss.
In the no-compromise time-nuts context, there may be a good place for a
Gilbert cell. Maybe in a circuit where the Gilbert cell is getting hit with
a well-defined signal with low dynamic range that dwarfs the noise
contribution. The low LO requirement of a Gilbert cell also makes it easier
to isolate the LO from the rest of the circuitry and that can reduce
shielding needs. But it's not gonna go where you need both low noise and
high dynamic range.
Tim N3QE
On Wed, Jan 6, 2016 at 9:30 PM, Richard (Rick) Karlquist <
richard@karlquist.com> wrote:
On 1/5/2016 12:07 PM, Bruce Griffiths wrote:
The noise of such Gilbert cell based analog multipliers far exceeds that
of the traditional mixer.
Bruce
Read Gilbert's paper or Gray and Meyers analog IC textbook and
you will see that the whole theory of operation of these
depends on keeping the signal levels in them very small,
especially if linearity (actually translinearity) is
important. They always have current sources in the
emitters that contribute a lot of noise. So you have
small signals and large noise. The IC's that are
designed to be DC coupled have even more sources of
extra noise.
IMHO, they only make sense in low performance applications
where the lack of transformers is important or in DC
coupled applications. The only time I have used an
analog multiplier IC was in Costas loop to demodulate
QPSK from weather satellite. It needed to be DC coupled.
Rick Karlquist N6RK
On Wednesday, 6 January 2016 9:01 AM, Poul-Henning Kamp <
phk@phk.freebsd.dk> wrote:
My little HP5065 project is continually running into the jitter of
my HP5370B counter which is annoying me, so I'm looking int DMTD.
Everybody seems to be using traditional diode-mixers for DMTD,
and to be honest I fail to see the attraction.
Why wouldn't a analog multiplier like AD835 be better idea ?
What am I overlooking ?
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Hi
If your intention is to run a mixer with saturated inputs …. just run
an X-OR gate. It will handle the high level signals much better than
an over-driven analog part.
Yes somebody should check out a board built that way …. I’ll
let you know when I do.
Bob
On Jan 7, 2016, at 7:35 AM, Attila Kinali attila@kinali.ch wrote:
On Wed, 6 Jan 2016 18:30:07 -0800
"Richard (Rick) Karlquist" richard@karlquist.com wrote:
Read Gilbert's paper or Gray and Meyers analog IC textbook and
you will see that the whole theory of operation of these
depends on keeping the signal levels in them very small,
especially if linearity (actually translinearity) is
important. They always have current sources in the
emitters that contribute a lot of noise. So you have
small signals and large noise. The IC's that are
designed to be DC coupled have even more sources of
extra noise.
How about using the Gilbert Cell as "digital" mixer,
ie driving the currents hard from one branch to the other
and replacing the current sources by resistors?
How much would that improve the noise? Would it be still much
worse than the diode mixer?
Attila Kinali
--
It is upon moral qualities that a society is ultimately founded. All
the prosperity and technological sophistication in the world is of no
use without that foundation.
-- Miss Matheson, The Diamond Age, Neil Stephenson
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On 1/7/2016 3:11 PM, Bob Camp wrote:
Hi
If your intention is to run a mixer with saturated inputs …. just run
an X-OR gate. It will handle the high level signals much better than
an over-driven analog part.
Bob
If you look at the schematic of an XOR gate IC and compare it
to the schematic of, for example, an MC1496 mixer, you will
see a lot of similarity. If the gate is of the ECL type,
it will have the addition of emitter followers, but that
it a minor detail of implementation. I'm not sure there
is a huge difference. ECL is a great logic family in
general (self-confessed ECL-phile here :-) but it is
probably the worst for phase noise, compared to the
saturating logic types.
Rick Karlquist N6RK
Hi
The board I have uses high speed CMOS single gate XOR’s. They have a pretty good
phase noise floor (-170’s) so they should be pretty reasonable.
Bob
On Jan 8, 2016, at 12:16 PM, Richard (Rick) Karlquist richard@karlquist.com wrote:
On 1/7/2016 3:11 PM, Bob Camp wrote:
Hi
If your intention is to run a mixer with saturated inputs …. just run
an X-OR gate. It will handle the high level signals much better than
an over-driven analog part.
Bob
If you look at the schematic of an XOR gate IC and compare it
to the schematic of, for example, an MC1496 mixer, you will
see a lot of similarity. If the gate is of the ECL type,
it will have the addition of emitter followers, but that
it a minor detail of implementation. I'm not sure there
is a huge difference. ECL is a great logic family in
general (self-confessed ECL-phile here :-) but it is
probably the worst for phase noise, compared to the
saturating logic types.
Rick Karlquist N6RK
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and follow the instructions there.
Hi Bob,
In some article, I see people use a D-flipflop to sample the input
signal with reference clock. When you want implement a mixer what's the
difference between D-flipflop and XOR gate? Acorrding to my understanding,
to multiply 1bit with another, I should use an AND gate, right?
When you refer high speed CMOS XOR gate, do you mean 74LVC1G86?
Thanks
BI7LNQ
2016-01-09 6:42 GMT+08:00 Bob Camp kb8tq@n1k.org:
Hi
The board I have uses high speed CMOS single gate XOR’s. They have a
pretty good
phase noise floor (-170’s) so they should be pretty reasonable.
Bob
On Jan 8, 2016, at 12:16 PM, Richard (Rick) Karlquist <
richard@karlquist.com> wrote:
On 1/7/2016 3:11 PM, Bob Camp wrote:
Hi
If your intention is to run a mixer with saturated inputs …. just run
an X-OR gate. It will handle the high level signals much better than
an over-driven analog part.
Bob
If you look at the schematic of an XOR gate IC and compare it
to the schematic of, for example, an MC1496 mixer, you will
see a lot of similarity. If the gate is of the ECL type,
it will have the addition of emitter followers, but that
it a minor detail of implementation. I'm not sure there
is a huge difference. ECL is a great logic family in
general (self-confessed ECL-phile here :-) but it is
probably the worst for phase noise, compared to the
saturating logic types.
Rick Karlquist N6RK
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and follow the instructions there.
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Hi
You can use a D flip flop to sample (down convert) a signal. You may or
may not get into metastability problems when you do.
If you treat the gate inputs as -1 and +1 rather than 0 and 1, the XOR is a
multiplier. If you put two signals into the gate and look at the output on a
spectrum analyzer, you get the expected multiplier output. The why of
the -1 and +1 stuff is something I will leave to others. It’s a bit involved.
The 74LVC is a good series to use. The NC7SZ series is also a good one.
In both cases, you will get a better noise floor at 5.5 V than at 3 V.
Bob
On Jan 8, 2016, at 9:19 PM, Li Ang lllaaa@gmail.com wrote:
Hi Bob,
In some article, I see people use a D-flipflop to sample the input
signal with reference clock. When you want implement a mixer what's the
difference between D-flipflop and XOR gate? Acorrding to my understanding,
to multiply 1bit with another, I should use an AND gate, right?
When you refer high speed CMOS XOR gate, do you mean 74LVC1G86?
Thanks
BI7LNQ
2016-01-09 6:42 GMT+08:00 Bob Camp kb8tq@n1k.org:
Hi
The board I have uses high speed CMOS single gate XOR’s. They have a
pretty good
phase noise floor (-170’s) so they should be pretty reasonable.
Bob
On Jan 8, 2016, at 12:16 PM, Richard (Rick) Karlquist <
richard@karlquist.com> wrote:
On 1/7/2016 3:11 PM, Bob Camp wrote:
Hi
If your intention is to run a mixer with saturated inputs …. just run
an X-OR gate. It will handle the high level signals much better than
an over-driven analog part.
Bob
If you look at the schematic of an XOR gate IC and compare it
to the schematic of, for example, an MC1496 mixer, you will
see a lot of similarity. If the gate is of the ECL type,
it will have the addition of emitter followers, but that
it a minor detail of implementation. I'm not sure there
is a huge difference. ECL is a great logic family in
general (self-confessed ECL-phile here :-) but it is
probably the worst for phase noise, compared to the
saturating logic types.
Rick Karlquist N6RK
time-nuts mailing list -- time-nuts@febo.com
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and follow the instructions there.
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On Sat, 9 Jan 2016 10:19:05 +0800
Li Ang lllaaa@gmail.com wrote:
In some article, I see people use a D-flipflop to sample the input
signal with reference clock. When you want implement a mixer what's the
difference between D-flipflop and XOR gate?
A D-Flipflop is a rather weird mixer. I have not done the calculation,
but i'm pretty sure that the output is not exactly what you'd expect
it from a normal mixer (namely having half the energy at the frequeny
difference and half at the sum).
An XOR gate on the other hand, produces a very nice spectrum, given
you input two clean square wave signals.
Acorrding to my understanding,
to multiply 1bit with another, I should use an AND gate, right?
If you think of the signals as digital in the computational sense,
with "high" representing "1" and "low" representing "0" then yes.
But in signal theory, it's more appropriate to think of signals
as "high" representing "+1" and low representing "-1".
In the latter case, the XOR is the multiplicative element, and not
the AND gate.
When you refer high speed CMOS XOR gate, do you mean 74LVC1G86?
Generally speaking: Faster CMOS better than slower CMOS in terms of phase noise.
(Though, I have yet to see actual measurements of this)
Single gate chips better than multi gate chips.
(no interference through the power supply of the different sub-parts)
Attila Kinali
--
It is upon moral qualities that a society is ultimately founded. All
the prosperity and technological sophistication in the world is of no
use without that foundation.
-- Miss Matheson, The Diamond Age, Neil Stephenson
Attila,
On 01/09/2016 09:25 PM, Attila Kinali wrote:
On Sat, 9 Jan 2016 10:19:05 +0800
Li Ang lllaaa@gmail.com wrote:
In some article, I see people use a D-flipflop to sample the input
signal with reference clock. When you want implement a mixer what's the
difference between D-flipflop and XOR gate?
A D-Flipflop is a rather weird mixer. I have not done the calculation,
but i'm pretty sure that the output is not exactly what you'd expect
it from a normal mixer (namely having half the energy at the frequeny
difference and half at the sum).
It's not that wierd. It's a sampler, and thus it acts like a mixer as if
the signal is spikes, which is just another interpretation of the
Nyquist frequency aliasing. Meta-stability however creates an
"interesting" aspect.
An XOR gate on the other hand, produces a very nice spectrum, given
you input two clean square wave signals.
Indeed.
An interesting variant of the XOR gate as being used as a mixer is when
you build a rubidium. One synthesis approach being used is to divide the
5 MHz OCXO signal with 16 to get 312,5 kHz. Then XORing it with 5 MHz
produces as one of it's mirror signals 5,3125 MHz which is then fed with
a step-up signal of 60 MHz or 90 MHz into the SDR diode in the cavity.
A third digital phase-detector is the SR flip-flop. It avoids the 180
degree phase property (really a triangle wave signal) of the XOR, but
give a 360 degree phase sawtooth. This can be helpful in certain lock-up
conditions.
The phase-frequency detector of the 4046 and the like has additional
flip-flops to remember slipped cycles and forcing the frequency to
regain that. Those provide a strong frequency lock mechanism with a
phase detector in one.
When you refer high speed CMOS XOR gate, do you mean 74LVC1G86?
Generally speaking: Faster CMOS better than slower CMOS in terms of phase noise.
(Though, I have yet to see actual measurements of this)
Single gate chips better than multi gate chips.
(no interference through the power supply of the different sub-parts)
Well, you should wire the other parts into passive mode.
Cheers,
Magnus
In message 20160109212523.39180e2b7a788fe1ee2d7a3a@kinali.ch, Attila Kinali
writes:
Single gate chips better than multi gate chips.
(no interference through the power supply of the different sub-parts)
Would paralleing multiple gates in the same chip make things
better or worse ?
--
Poul-Henning Kamp | UNIX since Zilog Zeus 3.20
phk@FreeBSD.ORG | TCP/IP since RFC 956
FreeBSD committer | BSD since 4.3-tahoe
Never attribute to malice what can adequately be explained by incompetence.
Hi
On Jan 9, 2016, at 3:25 PM, Attila Kinali attila@kinali.ch wrote:
Generally speaking: Faster CMOS better than slower CMOS in terms of phase noise.
(Though, I have yet to see actual measurements of this)
The gotcha is that each family gets measured as the parts come out. Thus the data
is spread out over about a 40+ year period. Most of it was taken down in log books
off of a screen ….
Bob
Single gate chips better than multi gate chips.
(no interference through the power supply of the different sub-parts)
Attila Kinali
--
It is upon moral qualities that a society is ultimately founded. All
the prosperity and technological sophistication in the world is of no
use without that foundation.
-- Miss Matheson, The Diamond Age, Neil Stephenson
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