DMTD - analog multiplier vs. diode mixer ?
God morgon,
On Sat, 9 Jan 2016 23:01:31 +0100
Magnus Danielson magnus@rubidium.dyndns.org wrote:
A D-Flipflop is a rather weird mixer. I have not done the calculation,
but i'm pretty sure that the output is not exactly what you'd expect
it from a normal mixer (namely having half the energy at the frequeny
difference and half at the sum).
It's not that wierd. It's a sampler, and thus it acts like a mixer as if
the signal is spikes, which is just another interpretation of the
Nyquist frequency aliasing. Meta-stability however creates an
"interesting" aspect.
Ah right! That also explains my uneasy feeling about it :-)
It's relatively easy to get around metastabilitiy: just add another
couple of D-flipflops in series. Unfortunately, that will only fix
the metastable lingering in-between. It wont fix the edge being at
the wrong time.
A third digital phase-detector is the SR flip-flop. It avoids the 180
degree phase property (really a triangle wave signal) of the XOR, but
give a 360 degree phase sawtooth. This can be helpful in certain lock-up
conditions.
SR-flipflop? Are you refering to the JK-FF phase detector or the PFD?
The phase-frequency detector of the 4046 and the like has additional
flip-flops to remember slipped cycles and forcing the frequency to
regain that. Those provide a strong frequency lock mechanism with a
phase detector in one.
Interesting... i have to look into the old datasheets.
Single gate chips better than multi gate chips.
(no interference through the power supply of the different sub-parts)
Well, you should wire the other parts into passive mode.
That would be a waste of good PCB space ;-)
Attila Kinali
--
It is upon moral qualities that a society is ultimately founded. All
the prosperity and technological sophistication in the world is of no
use without that foundation.
-- Miss Matheson, The Diamond Age, Neil Stephenson
Moin phk!
On Sat, 09 Jan 2016 22:56:27 +0000
"Poul-Henning Kamp" phk@phk.freebsd.dk wrote:
Single gate chips better than multi gate chips.
(no interference through the power supply of the different sub-parts)
Would paralleing multiple gates in the same chip make things
better or worse ?
Good question. I have no idea.
My first guess would be, that it would only give a slight improvement,
if at all.
The reasoning is the following:
Under the assumption that the noise of all gates is ergodic and stationary,
then averaging the outputs of the gates should reduce the output noise.
But the noise is not truly ergodic and there will be coupling between the
gates (both through the power supply and the outputs), that will change the
noise properties of the gates. Which in turn might lead to positive interference
of the noise, instead of averaging out.
But I have to admit that noise in electronic circuits is for me still
something very unintuitive. And I am more often wrong than right, when
it comes to predicting noise behaviour.
Attila Kinali
--
It is upon moral qualities that a society is ultimately founded. All
the prosperity and technological sophistication in the world is of no
use without that foundation.
-- Miss Matheson, The Diamond Age, Neil Stephenson
God eftermiddag,
On 01/10/2016 11:21 AM, Attila Kinali wrote:
God morgon,
On Sat, 9 Jan 2016 23:01:31 +0100
Magnus Danielson magnus@rubidium.dyndns.org wrote:
A D-Flipflop is a rather weird mixer. I have not done the calculation,
but i'm pretty sure that the output is not exactly what you'd expect
it from a normal mixer (namely having half the energy at the frequeny
difference and half at the sum).
It's not that wierd. It's a sampler, and thus it acts like a mixer as if
the signal is spikes, which is just another interpretation of the
Nyquist frequency aliasing. Meta-stability however creates an
"interesting" aspect.
Ah right! That also explains my uneasy feeling about it :-)
It's relatively easy to get around metastabilitiy: just add another
couple of D-flipflops in series. Unfortunately, that will only fix
the metastable lingering in-between. It wont fix the edge being at
the wrong time.
Indeed. The second DFF will reduce the noise induced by the
meta-stability. A small average shift in phase due to average
meta-stability time-shift isn't usually a bit problem.
However, it's down-mixing abilities is relatively straight-forward.
A third digital phase-detector is the SR flip-flop. It avoids the 180
degree phase property (really a triangle wave signal) of the XOR, but
give a 360 degree phase sawtooth. This can be helpful in certain lock-up
conditions.
SR-flipflop? Are you refering to the JK-FF phase detector or the PFD?
A straight SR-flipflop. I would have written JK-FF or PFD if I meant it.
Also, as I mentioned the PFD directly after, you could have concluded
that was not what I intended.
A SR-flip-flop with no illegal input states is easy to build from a 74HC00.
The phase-frequency detector of the 4046 and the like has additional
flip-flops to remember slipped cycles and forcing the frequency to
regain that. Those provide a strong frequency lock mechanism with a
phase detector in one.
Interesting... i have to look into the old datasheets.
It's really several SR flip-flops interconnected. It's intended to
simplify design with a "digital" core, it aids in frequency lock as it
pulls the integrator cap in the right direction stronger than the weak
beating does on a distance in frequency difference. This way, you
improve locking time for simple designs. There is other ways to aid the
loop known to the professional.
Single gate chips better than multi gate chips.
(no interference through the power supply of the different sub-parts)
Well, you should wire the other parts into passive mode.
That would be a waste of good PCB space ;-)
No. If you add noise through the other parts of the same chip, you will
waste more PCB space to work around it.
Cheers,
Magnus
On 01/10/2016 11:32 AM, Attila Kinali wrote:
Moin phk!
On Sat, 09 Jan 2016 22:56:27 +0000
"Poul-Henning Kamp" phk@phk.freebsd.dk wrote:
Single gate chips better than multi gate chips.
(no interference through the power supply of the different sub-parts)
Would paralleing multiple gates in the same chip make things
better or worse ?
Good question. I have no idea.
My first guess would be, that it would only give a slight improvement,
if at all.
The reasoning is the following:
Under the assumption that the noise of all gates is ergodic and stationary,
then averaging the outputs of the gates should reduce the output noise.
But the noise is not truly ergodic and there will be coupling between the
gates (both through the power supply and the outputs), that will change the
noise properties of the gates. Which in turn might lead to positive interference
of the noise, instead of averaging out.
But I have to admit that noise in electronic circuits is for me still
something very unintuitive. And I am more often wrong than right, when
it comes to predicting noise behaviour.
Signals couples so nicely through power-pins, as the parasitic
inductance work on them. This is also known as ground-bounce. It will
limit the properties, and already have. In some counters, it was
"convenient" from a layout perspective to use a double-comparator. The
ground-bounce formed one of the main limiting factors, so in the next
generation they used single comparators and a few other tricks and could
half the noise-limits of the counter.
Few "chips" (rather chip packages) includes internal decoupling caps,
but it has started to appear for some of the larger onces as it is the
only way to avoid the issues while pushing speed upwards.
If you feed the same signal to the different XOR gates in the same
package, wiring might cause some spread, but ground-bounce would connect
them such that "late" gates would be encouraged by "early" gates. It
will not be so "independent" anymore.
Sometimes this cross-talk can work for you, but often against you.
Unless you know exactly what you are doing, isolation is a good thing.
Cheers,
Magnus
Hi
On Jan 10, 2016, at 5:32 AM, Attila Kinali attila@kinali.ch wrote:
Moin phk!
On Sat, 09 Jan 2016 22:56:27 +0000
"Poul-Henning Kamp" phk@phk.freebsd.dk wrote:
Single gate chips better than multi gate chips.
(no interference through the power supply of the different sub-parts)
Would paralleing multiple gates in the same chip make things
better or worse ?
Good question. I have no idea.
My first guess would be, that it would only give a slight improvement,
if at all.
The reasoning is the following:
Under the assumption that the noise of all gates is ergodic and stationary,
then averaging the outputs of the gates should reduce the output noise.
But the noise is not truly ergodic and there will be coupling between the
gates (both through the power supply and the outputs), that will change the
noise properties of the gates. Which in turn might lead to positive interference
of the noise, instead of averaging out.
But I have to admit that noise in electronic circuits is for me still
something very unintuitive. And I am more often wrong than right, when
it comes to predicting noise behavior.
How do the gate outputs combine?
Often the “pull down” part of the gate is stronger than the “pull up” part of the gate.
If that’s what happens, you get an odd voting process rather than an average ….
( one gate says low, two gates say high, we go low ….)
Bob
Attila Kinali
--
It is upon moral qualities that a society is ultimately founded. All
the prosperity and technological sophistication in the world is of no
use without that foundation.
-- Miss Matheson, The Diamond Age, Neil Stephenson
time-nuts mailing list -- time-nuts@febo.com
To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts
and follow the instructions there.
Phase frequency detectors (starting with the legendary MC4044)
being made out of flip flops, had metastability and/or race
conditions. Motorola showed a block diagram made of gates,
as if it were combinatorial logic, but because of the feedback,
it is actually a state machine, as described in the MC4044
data sheet. It had a dead zone around zero phase that came
to light when Fairchild introduced the competing 11C44 PFD
using Eric Breeze's patent to fix the dead zone. The
11C44 data sheet showed their dead zone, vs Brand M.
Even that improved chip still had a "funny" zone, it just
never went to zero gain.
Fast forward to today, we are now seeing PFD's made
with samplers. They too have a bunch of issues with
phase noise floors. None of them come close to a mixer.
In the 5071A, I used a mixer as a phase detector that
had some flip flops only used for acquisition, so they
were non players in terms of phase noise. I still think
I would do that even if I had to do over 25 years later.
Rick Karlquist N6RK
On Sun, 10 Jan 2016 14:30:41 +0100
Magnus Danielson magnus@rubidium.dyndns.org wrote:
SR-flipflop? Are you refering to the JK-FF phase detector or the PFD?
A straight SR-flipflop. I would have written JK-FF or PFD if I meant it.
Also, as I mentioned the PFD directly after, you could have concluded
that was not what I intended.
A SR-flip-flop with no illegal input states is easy to build from a 74HC00.
The illegal input states were my concern, indeed. And a quick google
didn't show up anything to disperse these....not until I started reading
the 4046 datasheet in detail.
But there is one thing about the arangement of the SR FF in the 4046[1]
that bothers me:
Although S = R = 1 is valid, it does lead to the output oscillating
between 0 and 1.
Attila Kinali
[1] Ti CD74HC4046A Datasheet
http://www.ti.com/lit/ds/symlink/cd54hc4046a.pdf
--
It is upon moral qualities that a society is ultimately founded. All
the prosperity and technological sophistication in the world is of no
use without that foundation.
-- Miss Matheson, The Diamond Age, Neil Stephenson
"generate stable high -frequency signals with d flip-flops as digital
mixers ans all -IC low frequency phase -locked loop", by R.Treadway and
L.J. Reed, page 78 Electronic design 1 January 1972
Resistot array denounces D flip-flop mixer page 184 EDN 12 April 1990
digital frequency subtract or EDN 1 April 1981
Kamil Kraus: Die Arbeitsweise eines einfachen Digitalmischer, Seite 72
Elektronik Heft 24, 1980 a very good explanation of the function of the
digital mixer-- in German
Design ideas; D flip-flop sutracs frequencies by Richard Kochis,
Hewlett-PackardCo Ft. Collins ,CO, Gerald Flachs , New Mexico State
University, Las Cruces, END 15 April, 10981 page 149
Robert a Pease National Semiconductor Corp : Four ICs subtract
frequencies, EDN 1 April 1981
"Digitalis keverofokozat tervezese", Zombay Frerenc, Radiotechnika,
Seite 244 # 5 1996, a complete design of the digital mixer with
detailed theory and example in three consecutive issue of the magazine
Radiotechnika -- in Hungarian.
By using that literature I designed many frequency synthesizers
containing D flip-flops as a digital mixer
73
KJ6 UHN
Alex
[alias Dr.Dipl.Ing. Alexander Pummer, PCS Consultants]
US patents: many if you are interested I will send you a list
On 1/10/2016 10:56 AM, Attila Kinali wrote:
On Sun, 10 Jan 2016 14:30:41 +0100
Magnus Danielson magnus@rubidium.dyndns.org wrote:
SR-flipflop? Are you refering to the JK-FF phase detector or the PFD?
A straight SR-flipflop. I would have written JK-FF or PFD if I meant it.
Also, as I mentioned the PFD directly after, you could have concluded
that was not what I intended.
A SR-flip-flop with no illegal input states is easy to build from a 74HC00.
The illegal input states were my concern, indeed. And a quick google
didn't show up anything to disperse these....not until I started reading
the 4046 datasheet in detail.
But there is one thing about the arangement of the SR FF in the 4046[1]
that bothers me:
Although S = R = 1 is valid, it does lead to the output oscillating
between 0 and 1.
Attila Kinali
[1] Ti CD74HC4046A Datasheet
http://www.ti.com/lit/ds/symlink/cd54hc4046a.pdf
and there was also a frequency/phase detector from Analog Devices, which
took care about that dead zone
73
KJ6UHN
Alex
On 1/10/2016 10:53 AM, Richard (Rick) Karlquist wrote:
Phase frequency detectors (starting with the legendary MC4044)
being made out of flip flops, had metastability and/or race
conditions. Motorola showed a block diagram made of gates,
as if it were combinatorial logic, but because of the feedback,
it is actually a state machine, as described in the MC4044
data sheet. It had a dead zone around zero phase that came
to light when Fairchild introduced the competing 11C44 PFD
using Eric Breeze's patent to fix the dead zone. The
11C44 data sheet showed their dead zone, vs Brand M.
Even that improved chip still had a "funny" zone, it just
never went to zero gain.
Fast forward to today, we are now seeing PFD's made
with samplers. They too have a bunch of issues with
phase noise floors. None of them come close to a mixer.
In the 5071A, I used a mixer as a phase detector that
had some flip flops only used for acquisition, so they
were non players in terms of phase noise. I still think
I would do that even if I had to do over 25 years later.
Rick Karlquist N6RK
time-nuts mailing list -- time-nuts@febo.com
To unsubscribe, go to
https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts
and follow the instructions there.
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Am 10.01.2016 um 22:47 schrieb Alexander Pummer:
and there was also a frequency/phase detector from Analog Devices,
which took care about that dead zone
AD9901.
73
KJ6UHN
Alex
73, Gerhard, DK4XP