Scott,

Hard to say which is better at this point; there are a number
of variables, not the least of which is the intrinsic short-term
stability of the OCXO you use.

Do have a close look at James Miller's GPSDO:

http://www.jrmiller.demon.co.uk/projects/freqstd/frqstd.htm

I recently tested one and it makes it to 1e-13 at one day, which
is really nice for a simple, cheap, homebrew GPSDO.

/tvb

Scott, you have also:
http://w3ref.cfn.ist.utl.pt/cupido/reflock.html

lab grade consider using reflock II
for kits I think TAPR still has those...

Luis Cupido
ct1dmk.

Scott Burris wrote:

Tom Van Baak wrote:

Tom

What about the short term performance?
Its relatively easy to achieve a stability of 1E-13 for an averaging
time of 1 day, achieving good short or medium term stability is more
difficult.

If you want simplicity and higher performance you can do far better with
fewer parts,
An expensive high resolution DAC can be replaced with a software
sigma-delta DAC that has higher resolution.
The complex phase detector can be replaced with a D flipflop.
Add a microprocessor plus an opamp or 2 to filter and scale the EFC
voltage and thats about all thats required in addition to a good GPS
timing receiver.
For improved performance a hardware circuit to correct the PPS sawtooth
error will improve the medium term stability significantly when using a
high performance GPS timing receiver that provides an estimate of this
error.

Both the Brooks Shera and the James Miller designs have inadequate phase
error measurement resolution to achieve good short and medium term
stability.
However, this is only noticeable when using high performance GPS timing
receivers (M12+T, M12MT etc) and a high quality OCXO (10811A etc).

Bruce

On Dec 11, 2007 12:53 PM, Bruce Griffiths bruce.griffiths@xtra.co.nz
wrote:

OK, so for the DAC piece, why not just use an NXP LPC ARM chip for the
microcontroller, and use a 32bit PCM output followed by a low pass filter as
the VXCO EFC?  The DAC just needs high resolution, not accuracy, right?
Or would the switching noise from the processor modulate the control
voltage?
I would hope the filter would clean any such noise, but I'll be the first to
admit
that the farther we get into the analog domain, the more I'm out of my
comfort zone.

I'm still trying to wrap my brain around the phase detection piece of this.
I've studied the Shera controller with it's 24Mhz oscillator and divided
down
sample of the VXCO and I'm can't get past thinking that this ends up
adding jitter.  With more modern parts can't the phase be measured more
directly?  What about sampling both the VXCO and 1PPS at a 200MHZ rate?
That should determine the phase difference within no more than a 10ns
inaccuracy.

Or use a pulse stretching technique to amplify the short time intervals into
something
more easily measured, although that's beyond what I'm familiar with.

I've read the PTTI presentation about using a DS1020 delay line to
de-sawtooth the
1PPS signal -- that's a pretty interesting idea.  At least the chip is
available in Qty 1,
at $30!

It just seems that the designs I've seen could use a refresh with some more
modern
circuitry.  At the very least the Shera controller could have much of its
logic put into
a single CPLD these days.

Scott

Scott

Scott Burris wrote:

True, but a Sigma delta DAC has far superior performance to a PWM DAC or
a standard DAC especially when the long term stability is not critical
and a faast response isnt required.
NIST use sigma delta DACs in their precision AC waveform generator and
to calibrate their Johnson noise thermometer systems.

Its best to have the processor drive an external current steering switch
(74HC4053) to switch a stable current into the summing junction of an
inverting opamp.
If you want I can send you a suitable circuit schematic.
With a suitable circuit one can just use a voltage reference and a
resistor to set the current, a spare  analog switch can be used in
series with the feedback resistor to provide temperature compensation
(important for good short and medium term stability). HP/Agilent in
effect use a similar temperature compensated current steering technique
in their 34401A 6.5 digit DVM.
Ulrich has uses similar techniques albeit with the sigma delta DAC logic
implemented in a gate array to achieve high resolution and good short
term stability.
In this application the DAC need not respond as fast so it can be
implemented in software.

Eliminate such unnecessary cost and complexity with a single D flipflop
phase detector (D connected to 10MHz signal or a divided down
subharmonic thereof, CLK connected to PPS) the circuit will
automatically adapt to achieve a resolution determined by the PPS jitter
(picoseconds if you have a good enough PPS source, a few nanosec with a
sawtooth corrected PPS signal from an M12M timing receiver, a few tens
of nanosec with an uncorrected PPS signal from an M12M timing receiver).
Thus its resolution is far better than when using a 24MHz clock and its
also cheaper and the hardware is less complex. Using a 200MHz clock just
increases the cost and power consumption without significant benefit
over the simpler D flipflop phase detector.
However you will need to write suitable software to process the D
flipflop output samples.

Again easily done but more complex than required.

That is a very good idea for getting the maximum performance with a D
flipflop phase detector and an M12M or similar GPS timing receiver.
You can do far better when using GPS carrier phase disciplining
techniques and the GPS receiver has all the necessary high resolution
phase measurement circuitry built in.
However considerable software development is required together with a
GPS receiver that makes the GPS carrier phase measurement data available.

The Shera controller is a dead end, it doesnt have sufficient resolution
and whilst increasing its resolution is possible there are simpler,
better and cheaper ways to achieve this.

Bruce

Hi Bruce and Scott.

Simplicity is good but when using a CPLD or an FPGA no need to get
simple if a better design still fits inside the chip ;-)

Indeed those style of phase measuring schemes have far better
performance than the simple flip flop or similar.

I say this because I had all the logic on a CPLD to play with
so I tried a large number of phase locking schemes and
could compare them.

First of all the lock capture range can become a bit
independent of the integration time with a proportional phase lag
counting method. Some counting methods will inherently search for lock
when lock is lost. Some of those methods also have lock acquisition
times orders of magnitude smaller.

On the other hand on CPLD (or FPGA) complexity doesn't cost more as
this stuff is ultra extra small considering the size of
a today's CPLD (eg. maxII w/ 1570 macrocells). No matter what you do
a medium CPLD will be only used 10 to 20% not more.

What I use on the reflock II is a time lag counter from the 1pps to
next clock, and this value drive a dac. Only a small integration time
is done digitally and the large integration time if one requires that
is done with a classical R and C without any active components right
before the Vtune of the VCXO. Therefore not a big DAC resolution is
required (I use 12-14bit) since the averaging is on the outside in an
analog filter in which simple 64 seconds integration time will grant
you 6 bit more resolution.

It may look a strange combination of a modern devices and a old
fashioned filter but it had by far outperformed all the designs I could
test w/ microporcessors + dac (in which some noise did get through),
or lack stability.

Luis Cupido
ct1dmk.
http://w3ref.cfn.ist.utl.pt/cupido/

Bruce Griffiths wrote:

On Dec 11, 2007 3:53 PM, Bruce Griffiths bruce.griffiths@xtra.co.nz wrote:

You have made similar comments about I believe the same approach in
the past. I was wondering if you have ever sketched out a schematic,
even if only rough. Perhaps with a few suggested components to try
(i.e. DAC, Op-Amp) that would be a good starting point for anyone who
wanted to prototype and evaluate the performance of this approach.

It is beyond my elementary design abilities to convert your
description into a well implemented design on my own, but I would be
interested in try to at least see if I could construct an unit using
these suggested techniques.

-Michael

michael taylor wrote:

Michael

Will provide a suitable circuit schematic for the DAC portion by around
1300 UTC.
The circuit will be suitable for either a PWM or a sigma-delta DAC.
The design will also include the ability to set (by selecting the values
of a couple of resistors) the EFC range to suit most OCXOs.

A sigma-delta DAC has the advantage that its easier to filter its output
than that of an equivalent resolution PWM DAC.

Combining a pair of lower resolution DACs with a few resistors will
produce a higher resolution output, however there will be problems with
monotonicity (when the coarse DAC output changes) unless the system is
periodically calibrated to  accommodate drifts due to temperature and
time. This can of course be done in software (no need for external
trimmers) however the calibration circuitry adds considerable complexity.

When testing the sigma delta DAC concept in software start with a simple
first order sigma delta modulator and then try a second order modulator
(dont go to higher order than a 2nd order modulator as they arent
necessary for this application and stabilisation of high order
modulators adds considerable complexity and can be difficult to achieve).

A suitable D flipflop phase detector design will follow shortly thereafter.

Do you also want a circuit for a sawtooth corrector using one of the
Maxim/Dallas programmable delay lines?

You will need to write the software for the sawtooth corrector and for
the D flip flop phase detector.
However I can provide descriptions of what the software needs to do,
along with suggestions for suitable algorithms.

Bruce

Luis

Luis Cupido wrote:

Not true, the effective measurement noise is only a few percent less
than that of a single bit phase detector (D flipflop) better with an
infinite resolution phase detector so why bother.
Single bit and 3 level ADCs are widely used in radio astronomy as except
when interference is a problem, multibit ADCs offer no significant
advantage.

By all means try them, but why add the power consumption and complexity
of a CPLD if it offers little improvement in performance?

If you are going to use a CPLD you should also implement the processor
in the gate array as this reduces the PCB wiring complexity considerably.

Trying to do all the filtering with an analog filter restricts the range
of loop response times to relatively small values degrading the
performance of the better OCXOs considerably.
Achieving time constants of 100 sec or more is somewhat
expensive/impractical using resistors and capacitors.
Some analog filtering is required but most of the long term filtering
should be done by the processor.

Layout and isolation of the DAC from processor created noise are critical.

Bruce