Testing the TAC, and a question about ADEV
Hello
How could I test the time to analog converter
we talked few posts ago?
Something that can be done with things I have
or can easily find.
I was thinking that would be nice to try to
feed it with signals similar to the real ones,
but that can be controlled: PPS + 10MHz reference,
without the PPS tipical jitter.
To do so I was thinking to use the PPS from
one of the 2 FE5680 and the 10MHz from the
second ad use these to simulate the real signals.
I can tune the frequency of the Rb with the
serial interface (tested and working).
I'd like to verify both the resolution and
repeteability.
I was trying to figure the approx jitter
I will have using the Rb like I said above,
so I'm giving an eye to this diagram from
John Miles page: http://www.ke5fx.com/rb.htm
If I'm understanding correctly, that 5680
at 1s should have most of the jitter (95% +-2sigma)
into an interval +- 3.08x10^-11 wide, i.e. about 62pS
on the PPS signal (non considering the PPS buffer
inside the 5680). Is this how it work, or I'm mistaking?
This is from only one unit, but both unit will have
the jitter, how to take into account the jitter
from both?
Is there a better method to make this test?
I could try to test the TAC alone feeding it
with a 100 to 200nS pulse, but I dont know
from where to start to generate a clean stable
and repeteable pulse.
I have the 2 5680, the counter with it's 10MHz
inputs and outpus, and a Vectron OCXO that came
with one of the 5680, with these markings:
OCXO500-18 63.897600MHz
34537 A0715
and...
soldering iron, solder and scrap electronics :)
Thanks,
Fabio.
Fabio Eboli wrote:
Hello
How could I test the time to analog converter
we talked few posts ago?
Something that can be done with things I have
or can easily find.
One method is to use a statistical fill the buckets technique to measure
the linearity.
To do this one needs to use an incoherent source to trigger the
interpolator and plot a histogram of the results.
A noisy RC oscillator would be useful for this but care should be taken
to avoid injection locking.
To achieve useful measurement in a reasonable time interval a trigger
rate somewhat greater than 1Hz is required.
If the interpolator has 1024 time delay bins then ~ 100,000 trigger
events are required to achieve a bin width measurement error of 10%.
Otherwise a series of measurements of a set of accurately known delays
is required.
Useful results can be produced by measuring the delay between various
outputs of a shift register clocked at a sequence of different measured
frequencies.
I was thinking that would be nice to try to
feed it with signals similar to the real ones,
but that can be controlled: PPS + 10MHz reference,
without the PPS tipical jitter.
One should characterise the interpolator linearity etc first.
To do so I was thinking to use the PPS from
one of the 2 FE5680 and the 10MHz from the
second ad use these to simulate the real signals.
I can tune the frequency of the Rb with the
serial interface (tested and working).
I'd like to verify both the resolution and
repeteability.
I was trying to figure the approx jitter
I will have using the Rb like I said above,
so I'm giving an eye to this diagram from
John Miles page: http://www.ke5fx.com/rb.htm
If I'm understanding correctly, that 5680
at 1s should have most of the jitter (95% +-2sigma)
into an interval +- 3.08x10^-11 wide, i.e. about 62pS
on the PPS signal (non considering the PPS buffer
inside the 5680). Is this how it work, or I'm mistaking?
This is from only one unit, but both unit will have
the jitter, how to take into account the jitter
from both?
Is there a better method to make this test?
I could try to test the TAC alone feeding it
with a 100 to 200nS pulse, but I dont know
from where to start to generate a clean stable
and repeteable pulse.
You dont need one (see above) as long as you have the means to
accumulate the results of 100,000 measurements or preferably more.
I have the 2 5680, the counter with it's 10MHz
inputs and outpus, and a Vectron OCXO that came
with one of the 5680, with these markings:
OCXO500-18 63.897600MHz
34537 A0715
and...
soldering iron, solder and scrap electronics :)
Thanks,
Fabio.
Bruce
Hi
The statistical fill approach is a cute way to go. The gotcha comes in when you have a structure that may not be monotonic.
Bob
On Dec 28, 2012, at 1:04 PM, Bruce Griffiths bruce.griffiths@xtra.co.nz wrote:
Fabio Eboli wrote:
Hello
How could I test the time to analog converter
we talked few posts ago?
Something that can be done with things I have
or can easily find.
One method is to use a statistical fill the buckets technique to measure the linearity.
To do this one needs to use an incoherent source to trigger the interpolator and plot a histogram of the results.
A noisy RC oscillator would be useful for this but care should be taken to avoid injection locking.
To achieve useful measurement in a reasonable time interval a trigger rate somewhat greater than 1Hz is required.
If the interpolator has 1024 time delay bins then ~ 100,000 trigger events are required to achieve a bin width measurement error of 10%.
Otherwise a series of measurements of a set of accurately known delays is required.
Useful results can be produced by measuring the delay between various outputs of a shift register clocked at a sequence of different measured frequencies.
I was thinking that would be nice to try to
feed it with signals similar to the real ones,
but that can be controlled: PPS + 10MHz reference,
without the PPS tipical jitter.
One should characterise the interpolator linearity etc first.
To do so I was thinking to use the PPS from
one of the 2 FE5680 and the 10MHz from the
second ad use these to simulate the real signals.
I can tune the frequency of the Rb with the
serial interface (tested and working).
I'd like to verify both the resolution and
repeteability.
I was trying to figure the approx jitter
I will have using the Rb like I said above,
so I'm giving an eye to this diagram from
John Miles page: http://www.ke5fx.com/rb.htm
If I'm understanding correctly, that 5680
at 1s should have most of the jitter (95% +-2sigma)
into an interval +- 3.08x10^-11 wide, i.e. about 62pS
on the PPS signal (non considering the PPS buffer
inside the 5680). Is this how it work, or I'm mistaking?
This is from only one unit, but both unit will have
the jitter, how to take into account the jitter
from both?
Is there a better method to make this test?
I could try to test the TAC alone feeding it
with a 100 to 200nS pulse, but I dont know
from where to start to generate a clean stable
and repeteable pulse.
You dont need one (see above) as long as you have the means to accumulate the results of 100,000 measurements or preferably more.
I have the 2 5680, the counter with it's 10MHz
inputs and outpus, and a Vectron OCXO that came
with one of the 5680, with these markings:
OCXO500-18 63.897600MHz
34537 A0715
and...
soldering iron, solder and scrap electronics :)
Thanks,
Fabio.
Bruce
time-nuts mailing list -- time-nuts@febo.com
To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts
and follow the instructions there.
One potential source of non monotonicity is the ADC particularly those
embedded in a microprocessor.
The only cure being to either use an external ADC that is monotonic or
truncate the ADC result until it's monotonic.
Varying the synchroniser clock frequency (a 2:1 range should suffice to
cover the range of interest) should allow non monotonic behaviour to be
detected.
Otherwise one has to resort to using calibrated delay lines.
Bruce
Bob Camp wrote:
Hi
The statistical fill approach is a cute way to go. The gotcha comes in when you have a structure that may not be monotonic.
Bob
On Dec 28, 2012, at 1:04 PM, Bruce Griffithsbruce.griffiths@xtra.co.nz wrote:
Fabio Eboli wrote:
Hello
How could I test the time to analog converter
we talked few posts ago?
Something that can be done with things I have
or can easily find.
One method is to use a statistical fill the buckets technique to measure the linearity.
To do this one needs to use an incoherent source to trigger the interpolator and plot a histogram of the results.
A noisy RC oscillator would be useful for this but care should be taken to avoid injection locking.
To achieve useful measurement in a reasonable time interval a trigger rate somewhat greater than 1Hz is required.
If the interpolator has 1024 time delay bins then ~ 100,000 trigger events are required to achieve a bin width measurement error of 10%.
Otherwise a series of measurements of a set of accurately known delays is required.
Useful results can be produced by measuring the delay between various outputs of a shift register clocked at a sequence of different measured frequencies.
I was thinking that would be nice to try to
feed it with signals similar to the real ones,
but that can be controlled: PPS + 10MHz reference,
without the PPS tipical jitter.
One should characterise the interpolator linearity etc first.
To do so I was thinking to use the PPS from
one of the 2 FE5680 and the 10MHz from the
second ad use these to simulate the real signals.
I can tune the frequency of the Rb with the
serial interface (tested and working).
I'd like to verify both the resolution and
repeteability.
I was trying to figure the approx jitter
I will have using the Rb like I said above,
so I'm giving an eye to this diagram from
John Miles page: http://www.ke5fx.com/rb.htm
If I'm understanding correctly, that 5680
at 1s should have most of the jitter (95% +-2sigma)
into an interval +- 3.08x10^-11 wide, i.e. about 62pS
on the PPS signal (non considering the PPS buffer
inside the 5680). Is this how it work, or I'm mistaking?
This is from only one unit, but both unit will have
the jitter, how to take into account the jitter
from both?
Is there a better method to make this test?
I could try to test the TAC alone feeding it
with a 100 to 200nS pulse, but I dont know
from where to start to generate a clean stable
and repeteable pulse.
You dont need one (see above) as long as you have the means to accumulate the results of 100,000 measurements or preferably more.
I have the 2 5680, the counter with it's 10MHz
inputs and outpus, and a Vectron OCXO that came
with one of the 5680, with these markings:
OCXO500-18 63.897600MHz
34537 A0715
and...
soldering iron, solder and scrap electronics :)
Thanks,
Fabio.
Bruce
time-nuts mailing list -- time-nuts@febo.com
To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts
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and follow the instructions there.
Hi Fabio,
On 28/12/12 17:26, Fabio Eboli wrote:
Hello
How could I test the time to analog converter
we talked few posts ago?
Something that can be done with things I have
or can easily find.
I was thinking that would be nice to try to
feed it with signals similar to the real ones,
but that can be controlled: PPS + 10MHz reference,
without the PPS tipical jitter.
To do so I was thinking to use the PPS from
one of the 2 FE5680 and the 10MHz from the
second ad use these to simulate the real signals.
Not a bad approach.
Recall that you do not need to run it as seldom as 1s, you can run it
more often. You can allow for a wide set of frequency offsets that way.
I can tune the frequency of the Rb with the
serial interface (tested and working).
I'd like to verify both the resolution and
repeteability.
It should be a good way to sweep through the various delays in a
sequence, which with fairly simple post-processing would reveal both the
jitter and non-linearity.
I was trying to figure the approx jitter
I will have using the Rb like I said above,
so I'm giving an eye to this diagram from
John Miles page: http://www.ke5fx.com/rb.htm
If I'm understanding correctly, that 5680
at 1s should have most of the jitter (95% +-2sigma)
into an interval +- 3.08x10^-11 wide, i.e. about 62pS
on the PPS signal (non considering the PPS buffer
inside the 5680). Is this how it work, or I'm mistaking?
This is from only one unit, but both unit will have
the jitter, how to take into account the jitter
from both?
Noise jitter adds like power, so same noise would give you a 1.41
multiplication up.
Is there a better method to make this test?
I could try to test the TAC alone feeding it
with a 100 to 200nS pulse, but I dont know
from where to start to generate a clean stable
and repeteable pulse.
Having two 5680s isn't a bad solution, as you can tweak one of them to
be a suitable rate off from the other to slowly sweep the range.
Processing of that should allow you to characterize your interpolator
with not to much of coding magic. By measuring over longer period would
allow you to see just how temperature-sensitive you are.
So, you just want to produce a 1 PPS, so a PIC divider such as TADD-2
would be suitable if you don't have PPSes on your 5680s.
I have the 2 5680, the counter with it's 10MHz
inputs and outpus, and a Vectron OCXO that came
with one of the 5680, with these markings:
OCXO500-18 63.897600MHz
34537 A0715
and...
soldering iron, solder and scrap electronics :)
You could do a bit of damage with that :)
Cheers,
Magnus
Bruce, Bob, now I have more questions
than before :)
First and most important:
Where can I find references about the
statistical method you mentioned?
I tried to search online but didnt't find
any info.
What do you think about the simple setup
I mentioned before (the 2 Rb osc)?
If I set accurately the frequency difference
(easy with a scope and a timer) I will know
the cycle-by-cycle pulse increment
(or reduction).
Was the jitter estimation I made
for the single Rb correct?
Fabio.
P.S. The micro's adc is charachterized
for total unadjusted error of +-2LSB Max
at 25°C, 12bit total.
It's s-h is 8pF with 1kohm in series,
probably I can sync the sampling to
open just before the pulse, and close
after the fact.
Il 2012-12-28 19:53 Bruce Griffiths ha scritto:
One potential source of non monotonicity is the ADC particularly
those embedded in a microprocessor.
The only cure being to either use an external ADC that is monotonic
or truncate the ADC result until it's monotonic.
Varying the synchroniser clock frequency (a 2:1 range should suffice
to cover the range of interest) should allow non monotonic behaviour
to be detected.
Otherwise one has to resort to using calibrated delay lines.
Bruce
Bob Camp wrote:
Hi
The statistical fill approach is a cute way to go. The gotcha comes
in when you have a structure that may not be monotonic.
Bob
On Dec 28, 2012, at 1:04 PM, Bruce
Griffithsbruce.griffiths@xtra.co.nz wrote:
Fabio Eboli wrote:
Hello
How could I test the time to analog converter
we talked few posts ago?
Something that can be done with things I have
or can easily find.
One method is to use a statistical fill the buckets technique to
measure the linearity.
To do this one needs to use an incoherent source to trigger the
interpolator and plot a histogram of the results.
A noisy RC oscillator would be useful for this but care should be
taken to avoid injection locking.
To achieve useful measurement in a reasonable time interval a
trigger rate somewhat greater than 1Hz is required.
If the interpolator has 1024 time delay bins then ~ 100,000 trigger
events are required to achieve a bin width measurement error of 10%.
Otherwise a series of measurements of a set of accurately known
delays is required.
Useful results can be produced by measuring the delay between
various outputs of a shift register clocked at a sequence of
different measured frequencies.
I was thinking that would be nice to try to
feed it with signals similar to the real ones,
but that can be controlled: PPS + 10MHz reference,
without the PPS tipical jitter.
One should characterise the interpolator linearity etc first.
To do so I was thinking to use the PPS from
one of the 2 FE5680 and the 10MHz from the
second ad use these to simulate the real signals.
I can tune the frequency of the Rb with the
serial interface (tested and working).
I'd like to verify both the resolution and
repeteability.
I was trying to figure the approx jitter
I will have using the Rb like I said above,
so I'm giving an eye to this diagram from
John Miles page: http://www.ke5fx.com/rb.htm
If I'm understanding correctly, that 5680
at 1s should have most of the jitter (95% +-2sigma)
into an interval +- 3.08x10^-11 wide, i.e. about 62pS
on the PPS signal (non considering the PPS buffer
inside the 5680). Is this how it work, or I'm mistaking?
This is from only one unit, but both unit will have
the jitter, how to take into account the jitter
from both?
Is there a better method to make this test?
I could try to test the TAC alone feeding it
with a 100 to 200nS pulse, but I dont know
from where to start to generate a clean stable
and repeteable pulse.
You dont need one (see above) as long as you have the means to
accumulate the results of 100,000 measurements or preferably more.
I have the 2 5680, the counter with it's 10MHz
inputs and outpus, and a Vectron OCXO that came
with one of the 5680, with these markings:
OCXO500-18 63.897600MHz
34537 A0715
and...
soldering iron, solder and scrap electronics :)
Thanks,
Fabio.
Bruce
time-nuts mailing list -- time-nuts@febo.com
To unsubscribe, go to
https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts
and follow the instructions there.
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To unsubscribe, go to
https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts
and follow the instructions there.
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To unsubscribe, go to
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and follow the instructions there.
Little update about the PA6H GPS.
I was having problems with periodic abrutp change in drift.
I didnt like the psu of the Rb, so modifed them and started
logging temperature and voltages.
Now I have some early evidence of the suspect: the GPS receiver
seem upset by rapid changes in temperature.
When I have a temperature variation on the GPS, I see a drift
change in the PPS logged signal (against Rb reference).
It seems that the drift changes by a magnitute proportional
to the rate of change in temperature (dT/dt).
Is this something I should expect from a GPS receiver or is
a "feature" of my model? What process could generate this problem?
It's like if there is a big delay in the pulse inside the module,
that is temperature dependent and changes with unit temperature,
driving the PPS back and forth several 100's of nS when the temperature
changes.
I should "ballast" thermally the GPS, or I will have to thermostabilize
it :(
Hello Magnus,
It should be a good way to sweep through the various delays in a
sequence, which with fairly simple post-processing would reveal both
the jitter and non-linearity.
I've seen that with the scope I can set the two
Rb to march the edges almost exactly.
Noise jitter adds like power, so same noise would give you a 1.41
multiplication up.
So if my units are like the one in that test,
I will have somewhere around 90pS for 95% of the
samples. Not Bad.
So, you just want to produce a 1 PPS, so a PIC divider such as TADD-2
would be suitable if you don't have PPSes on your 5680s.
Fortunately my units have the PPS, I'm also
thinking to mod them and remove the LP filter
on 10MHz so I can have the logic level edge
without squaring the signal.
soldering iron, solder and scrap electronics :)
You could do a bit of damage with that :)
No need of these things to to damages, when
I was child some fertilizer and too much curiosity was enough...
I survived a pair of "near miss" events before I changed interests :)
On 28/12/12 20:33, Fabio Eboli wrote:
Bruce, Bob, now I have more questions
than before :)
First and most important:
Where can I find references about the
statistical method you mentioned?
I tried to search online but didnt't find
any info.
The bucket statistic method is very simple.
You divide a scale into a suitable set of ranges, equally wide. The you
count how many "hits" you get within each of those ranges or "buckets".
As your oscillators drift in phase relative to each other, you could
divide that into say 1024 "buckets". In this case, you would choose the
scale to stretch over the range of ADC values. Another way would be to
stretch them over the saw-tooth ramp.
What do you think about the simple setup
I mentioned before (the 2 Rb osc)?
If I set accurately the frequency difference
(easy with a scope and a timer) I will know
the cycle-by-cycle pulse increment
(or reduction).
Yes. If you have a 1 s rate of measurement, dial in 1E-11 in frequency
error, the advancement will be 10 ps (1E-11 s). The increment will be
y*T where y is the relative frequency error and T is the interval.
Cheers,
Magnus
On Fri, 28 Dec 2012 13:24:03 -0500
Bob Camp lists@rtty.us wrote:
The statistical fill approach is a cute way to go.
The gotcha comes in when you have a structure that may not be monotonic.
What does monotonic, or rather non-monotonic mean in this context?
Although i know what the word means, i dont get what it means in
terms of electronic behaviour in a TAC.
Attila Kinali
--
There is no secret ingredient
-- Po, Kung Fu Panda
Hi
Glitches are not very likely in a capacitor charge setup. FPGA TDC's have a lot of them. The "easy" way to find out you have a problem is to run multiple gizmos on the same set of inputs. Knowing you have a problem isn't always the same as solving the problem ….
Bob
On Dec 28, 2012, at 1:53 PM, Bruce Griffiths bruce.griffiths@xtra.co.nz wrote:
One potential source of non monotonicity is the ADC particularly those embedded in a microprocessor.
The only cure being to either use an external ADC that is monotonic or truncate the ADC result until it's monotonic.
Varying the synchroniser clock frequency (a 2:1 range should suffice to cover the range of interest) should allow non monotonic behaviour to be detected.
Otherwise one has to resort to using calibrated delay lines.
Bruce
Bob Camp wrote:
Hi
The statistical fill approach is a cute way to go. The gotcha comes in when you have a structure that may not be monotonic.
Bob
On Dec 28, 2012, at 1:04 PM, Bruce Griffithsbruce.griffiths@xtra.co.nz wrote:
Fabio Eboli wrote:
Hello
How could I test the time to analog converter
we talked few posts ago?
Something that can be done with things I have
or can easily find.
One method is to use a statistical fill the buckets technique to measure the linearity.
To do this one needs to use an incoherent source to trigger the interpolator and plot a histogram of the results.
A noisy RC oscillator would be useful for this but care should be taken to avoid injection locking.
To achieve useful measurement in a reasonable time interval a trigger rate somewhat greater than 1Hz is required.
If the interpolator has 1024 time delay bins then ~ 100,000 trigger events are required to achieve a bin width measurement error of 10%.
Otherwise a series of measurements of a set of accurately known delays is required.
Useful results can be produced by measuring the delay between various outputs of a shift register clocked at a sequence of different measured frequencies.
I was thinking that would be nice to try to
feed it with signals similar to the real ones,
but that can be controlled: PPS + 10MHz reference,
without the PPS tipical jitter.
One should characterise the interpolator linearity etc first.
To do so I was thinking to use the PPS from
one of the 2 FE5680 and the 10MHz from the
second ad use these to simulate the real signals.
I can tune the frequency of the Rb with the
serial interface (tested and working).
I'd like to verify both the resolution and
repeteability.
I was trying to figure the approx jitter
I will have using the Rb like I said above,
so I'm giving an eye to this diagram from
John Miles page: http://www.ke5fx.com/rb.htm
If I'm understanding correctly, that 5680
at 1s should have most of the jitter (95% +-2sigma)
into an interval +- 3.08x10^-11 wide, i.e. about 62pS
on the PPS signal (non considering the PPS buffer
inside the 5680). Is this how it work, or I'm mistaking?
This is from only one unit, but both unit will have
the jitter, how to take into account the jitter
from both?
Is there a better method to make this test?
I could try to test the TAC alone feeding it
with a 100 to 200nS pulse, but I dont know
from where to start to generate a clean stable
and repeteable pulse.
You dont need one (see above) as long as you have the means to accumulate the results of 100,000 measurements or preferably more.
I have the 2 5680, the counter with it's 10MHz
inputs and outpus, and a Vectron OCXO that came
with one of the 5680, with these markings:
OCXO500-18 63.897600MHz
34537 A0715
and...
soldering iron, solder and scrap electronics :)
Thanks,
Fabio.
Bruce
time-nuts mailing list -- time-nuts@febo.com
To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts
and follow the instructions there.
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To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts
and follow the instructions there.
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To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts
and follow the instructions there.