High rate, high precision/accuracy time interval counter methods
Hi,
We had here a discussion about measuring events (ie time stamping
them precisely) with high rates. As some of you know, Javier and
his group, Bruce and me are working on a system that should give
us something better than 10ps (my guess is that we should get close
to 1ps) at a rate of (guestimated) 1MHz per channel. (Based on the
excitation of a LC tank and measuring the ring-down/phase with an ADC).
As it is with researches, we want the moon, and prossible even more.
So we were talking about getting the measurement rate up even higher,
to 10MHz and if possible 50MHz with the same precision. The above
approche will not work above 1MHz. Using different filters it might
be possible to get it up to maybe 10MHz, but it would be an awkward
design at best.
The only methods I am aware of (and could find) that achieve such high
rates are those, based on (vernier) delay lines (and their equivalent
ring oscillator ones) in ASICs. But this means that a costly ASIC needs
to be produced.
Does someone know of other methods that could achieve high measurements
rates with better than 10ps precision/accuracy? (This question is mostly
a hypothetical question out of interest, I don't plan to build one...yet :-)
Attila Kinali
--
It is upon moral qualities that a society is ultimately founded. All
the prosperity and technological sophistication in the world is of no
use without that foundation.
-- Miss Matheson, The Diamond Age, Neil Stephenson
HP/Agilent/Keysight laser interferometers
measure at the kind of rates you are talking
about and (last time I heard) could divide
an interference fringe down to 1/512 of a
wavelength. As you say, they definitely use
an ASIC with a ring oscillator. Perhaps
there is some way you could repurpose the
interferometer electronics to make your
measurement.
You also might consider that over 25 years
ago, HP developed the 5313X counters with
interpolators implemented in FPGA's. The
FPGA's available now are vastly more
sophisticated and much faster. Perhaps there
is a way you do your ASIC in an FPGA.
If you really do need an ASIC, the best way
to get that done is to partner with a university
and have some PhD student design it. Universities
often have arrangements to do this.
Rick
On 5/3/2016 5:31 AM, Attila Kinali wrote:
Hi,
We had here a discussion about measuring events (ie time stamping
them precisely) with high rates. As some of you know, Javier and
his group, Bruce and me are working on a system that should give
us something better than 10ps (my guess is that we should get close
to 1ps) at a rate of (guestimated) 1MHz per channel. (Based on the
excitation of a LC tank and measuring the ring-down/phase with an ADC).
As it is with researches, we want the moon, and prossible even more.
So we were talking about getting the measurement rate up even higher,
to 10MHz and if possible 50MHz with the same precision. The above
approche will not work above 1MHz. Using different filters it might
be possible to get it up to maybe 10MHz, but it would be an awkward
design at best.
The only methods I am aware of (and could find) that achieve such high
rates are those, based on (vernier) delay lines (and their equivalent
ring oscillator ones) in ASICs. But this means that a costly ASIC needs
to be produced.
Does someone know of other methods that could achieve high measurements
rates with better than 10ps precision/accuracy? (This question is mostly
a hypothetical question out of interest, I don't plan to build one...yet :-)
Attila Kinali
Hi Attila,
On 05/03/2016 02:31 PM, Attila Kinali wrote:
Hi,
We had here a discussion about measuring events (ie time stamping
them precisely) with high rates. As some of you know, Javier and
his group, Bruce and me are working on a system that should give
us something better than 10ps (my guess is that we should get close
to 1ps) at a rate of (guestimated) 1MHz per channel. (Based on the
excitation of a LC tank and measuring the ring-down/phase with an ADC).
As it is with researches, we want the moon, and prossible even more.
So we were talking about getting the measurement rate up even higher,
to 10MHz and if possible 50MHz with the same precision. The above
approche will not work above 1MHz. Using different filters it might
be possible to get it up to maybe 10MHz, but it would be an awkward
design at best.
Getting to those rates will be challenging, especially with the LC tank.
For the higher rates a more traditional interpolator needs to be used,
charge a cap with the error pulse and sample that.
The only methods I am aware of (and could find) that achieve such high
rates are those, based on (vernier) delay lines (and their equivalent
ring oscillator ones) in ASICs. But this means that a costly ASIC needs
to be produced.
13.3 MHz (or every 75 ns) is achievable with the HP5372A, but it had
relatively meager single-shot resolution, 200 ps, compared to its
predecessor. It uses the delay vernier approach rather than the
triggered oscillator vernier (HP5370A/B) just because of sample-rate.
The HP5371A/5372A is made to analyze jitter rather than high resolution
long term stuff. Even as the limit shifts over time, high speed will end
up having somewhat lower resolution than a lower rate could offer.
However, with higher rate, you can use the least-square methods of mine
to get results and fight the white noise that way.
Does someone know of other methods that could achieve high measurements
rates with better than 10ps precision/accuracy? (This question is mostly
a hypothetical question out of interest, I don't plan to build one...yet :-)
Well, if you sample at sufficiently high rate, you can estimate the
rising/falling edge using least-square methods and then interpolate the
position. There is only a relatively small burst of samples needed, and
the least-square processing can be done using high-speed FPGA methods
similar to what is found in the article I sent you.
An alternative to the edge estimator method is to continuously sample,
mix with a reference frequency, decimate and then do arc-tangent of the
I/Q samples. This is what is used for phase-noise measurement such as
the Symmetricom/Microsemi test-kits, TimePod, and also the new R&S
phase-noise system. The phase values can be produced at very high rates
there and the noise of such setups can be maintained relatively low
compared to the comparator systems. For such systems the noise per
phase-sample is maybe even better understood as the averaging time over
the phase vs. noise is relatively simple process to understand.
Pipeline CORDIC can be used for arctan processing.
Cheers,
Magnus
Wouldn't this be a natural application of a centroid or transition
midpoint timing TDC implemented with a pulse shaper, fast ADC, and
FPGA?
What about sampling inphase and quadrature sine waves? This should be
more amendable to a microcontroller only solution and if I had to
start working on something immediately, this is what I would try
first.
I assume in the earlier discussion Bruce mentioned these methods since
they are included on his page of the various ways to implement TDCs:
http://www.ko4bb.com/~bruce/TDC.html
On Tue, 3 May 2016 08:40:53 -0700, you wrote:
HP/Agilent/Keysight laser interferometers
measure at the kind of rates you are talking
about and (last time I heard) could divide
an interference fringe down to 1/512 of a
wavelength. As you say, they definitely use
an ASIC with a ring oscillator. Perhaps
there is some way you could repurpose the
interferometer electronics to make your
measurement.
You also might consider that over 25 years
ago, HP developed the 5313X counters with
interpolators implemented in FPGA's. The
FPGA's available now are vastly more
sophisticated and much faster. Perhaps there
is a way you do your ASIC in an FPGA.
If you really do need an ASIC, the best way
to get that done is to partner with a university
and have some PhD student design it. Universities
often have arrangements to do this.
Rick
Rick,
Unless you uses the high-speed SERDES blocks, the jitter and systematic
noises inside FGPAs can be pretty prohibitive.
Enrico Rubiola and his team have made some of the best characterizations
of FPGAs I've seen, but I know from several other experinces that timing
can uhm shift around.
I proposed some 10 years ago to use the 10 Gb/s SERDES for 100 ps
resolution counter, the chip that could support it then could do 8
channels. It had some fancy tweaking so you could fine-tune the sampling
point to align channels up. Would still be a fun project to do.
The normal logic path isn't "as fun".
I'd say that the precision timing stuff should be done in a separate
front-end, but the sea of logic to handle all the dataflows can be done
in a FPGA.
Cheers,
Magnus
On 05/03/2016 05:40 PM, Richard (Rick) Karlquist wrote:
HP/Agilent/Keysight laser interferometers
measure at the kind of rates you are talking
about and (last time I heard) could divide
an interference fringe down to 1/512 of a
wavelength. As you say, they definitely use
an ASIC with a ring oscillator. Perhaps
there is some way you could repurpose the
interferometer electronics to make your
measurement.
You also might consider that over 25 years
ago, HP developed the 5313X counters with
interpolators implemented in FPGA's. The
FPGA's available now are vastly more
sophisticated and much faster. Perhaps there
is a way you do your ASIC in an FPGA.
If you really do need an ASIC, the best way
to get that done is to partner with a university
and have some PhD student design it. Universities
often have arrangements to do this.
Rick
On 5/3/2016 5:31 AM, Attila Kinali wrote:
Hi,
We had here a discussion about measuring events (ie time stamping
them precisely) with high rates. As some of you know, Javier and
his group, Bruce and me are working on a system that should give
us something better than 10ps (my guess is that we should get close
to 1ps) at a rate of (guestimated) 1MHz per channel. (Based on the
excitation of a LC tank and measuring the ring-down/phase with an ADC).
As it is with researches, we want the moon, and prossible even more.
So we were talking about getting the measurement rate up even higher,
to 10MHz and if possible 50MHz with the same precision. The above
approche will not work above 1MHz. Using different filters it might
be possible to get it up to maybe 10MHz, but it would be an awkward
design at best.
The only methods I am aware of (and could find) that achieve such high
rates are those, based on (vernier) delay lines (and their equivalent
ring oscillator ones) in ASICs. But this means that a costly ASIC needs
to be produced.
Does someone know of other methods that could achieve high measurements
rates with better than 10ps precision/accuracy? (This question is mostly
a hypothetical question out of interest, I don't plan to build
one...yet :-)
Attila Kinali
time-nuts mailing list -- time-nuts@febo.com
To unsubscribe, go to
https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts
and follow the instructions there.
I&Q sine sampling works, but a continuous sampling allows for N samples
to reduce the noise by sqrt(N) rather than 2 samples. The white-noise
will be the limiting factor for the higher rates.
Least-square estimation provides a 2.5 dB improvement over straight
sample average.
Cheers,
Magnus
On 05/03/2016 10:33 PM, David wrote:
Wouldn't this be a natural application of a centroid or transition
midpoint timing TDC implemented with a pulse shaper, fast ADC, and
FPGA?
What about sampling inphase and quadrature sine waves? This should be
more amendable to a microcontroller only solution and if I had to
start working on something immediately, this is what I would try
first.
I assume in the earlier discussion Bruce mentioned these methods since
they are included on his page of the various ways to implement TDCs:
http://www.ko4bb.com/~bruce/TDC.html
On Tue, 3 May 2016 08:40:53 -0700, you wrote:
HP/Agilent/Keysight laser interferometers
measure at the kind of rates you are talking
about and (last time I heard) could divide
an interference fringe down to 1/512 of a
wavelength. As you say, they definitely use
an ASIC with a ring oscillator. Perhaps
there is some way you could repurpose the
interferometer electronics to make your
measurement.
You also might consider that over 25 years
ago, HP developed the 5313X counters with
interpolators implemented in FPGA's. The
FPGA's available now are vastly more
sophisticated and much faster. Perhaps there
is a way you do your ASIC in an FPGA.
If you really do need an ASIC, the best way
to get that done is to partner with a university
and have some PhD student design it. Universities
often have arrangements to do this.
Rick
time-nuts mailing list -- time-nuts@febo.com
To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts
and follow the instructions there.
On Tuesday, May 03, 2016 02:31:17 PM Attila Kinali wrote:
Hi,
We had here a discussion about measuring events (ie time stamping
them precisely) with high rates. As some of you know, Javier and
his group, Bruce and me are working on a system that should give
us something better than 10ps (my guess is that we should get close
to 1ps) at a rate of (guestimated) 1MHz per channel. (Based on the
excitation of a LC tank and measuring the ring-down/phase with an ADC).
As it is with researches, we want the moon, and prossible even more.
So we were talking about getting the measurement rate up even higher,
to 10MHz and if possible 50MHz with the same precision. The above
approche will not work above 1MHz. Using different filters it might
be possible to get it up to maybe 10MHz, but it would be an awkward
design at best.
The only methods I am aware of (and could find) that achieve such high
rates are those, based on (vernier) delay lines (and their equivalent
ring oscillator ones) in ASICs. But this means that a costly ASIC needs
to be produced.
Does someone know of other methods that could achieve high measurements
rates with better than 10ps precision/accuracy? (This question is mostly
a hypothetical question out of interest, I don't plan to build one...yet :-)
Attila Kinali
Massive parallelism of a simple NUTT style interpolator (charge capacitor with
say 10mA, rundown with say 1uA, use 100MHz clock or faster clock ).
With a custom IC for the analog part, a resolution of 1ps should be feasible.
An FPGA can do all the non critical stuff like the rundown counting.
The problem is to ensure that the front end logic that selects the next non-
busy interpolator doesn't accumulate excessive jitter from cascaded gates.
The same issue of accumulated jitter produced by cascaded gates/inverters can
limit the performance of vernier delay line style interpolators. Minimising
the number of series inverters by using a higher frequency clock (100MHZ,
1GHz??) should help somewhat.
Bruce
On Tue, 3 May 2016 08:40:53 -0700
"Richard (Rick) Karlquist" richard@karlquist.com wrote:
You also might consider that over 25 years
ago, HP developed the 5313X counters with
interpolators implemented in FPGA's. The
FPGA's available now are vastly more
sophisticated and much faster. Perhaps there
is a way you do your ASIC in an FPGA.
The limit for TDCs in FPGAs seems to be around 5-20ps RMS
(which makes it more like 15-50ps in "real" precision)
depending on type and technology. Going down to below 20ps
usually means to take the latest tech FPGA with lots of
redundant structures, which makes the whole thing quite expensive.
If you really do need an ASIC, the best way
to get that done is to partner with a university
and have some PhD student design it. Universities
often have arrangements to do this.
Yes. That's one approach. And actually, we are currently going
that way for one of the projects I am doing. The problem with this
is that it's not exactly cheap (you need 10k at least to do anything)
and that any commercial use (like selling the chips to someone else
unless it's an academic institute again) is strictly prohibited.
Not to mention very limited availability (you get 40 pieces and that's it)
I was looking for something that can be produced more generally.
Possibly even by a dedicated hobbyist.
Attila Kinali
--
Reading can seriously damage your ignorance.
-- unknown
On Tue, 3 May 2016 22:31:14 +0200
Magnus Danielson magnus@rubidium.dyndns.org wrote:
An alternative to the edge estimator method is to continuously sample,
mix with a reference frequency, decimate and then do arc-tangent of the
I/Q samples. This is what is used for phase-noise measurement such as
the Symmetricom/Microsemi test-kits, TimePod, and also the new R&S
phase-noise system.
The "signal" is not a sinusoid, but discrete events. Think of it
as incomming pulses and you want to measure their arrival time.
Attila Kinali
--
Reading can seriously damage your ignorance.
-- unknown
Integrating A Time interval to charge TAC at the front end of a capacitive charge redistribution SAR ADC should allow a conversion time of 300ns or so.. Using 16 such TDCs should permit 1ps resolution with a 50MHz timestamp rate without too many cascaded gates in the selection logic for the next available TAC.
Bruce
On Wednesday, 4 May 2016 12:00 PM, Bruce Griffiths <bruce.griffiths@xtra.co.nz> wrote:
On Tuesday, May 03, 2016 02:31:17 PM Attila Kinali wrote:
Hi,
We had here a discussion about measuring events (ie time stamping
them precisely) with high rates. As some of you know, Javier and
his group, Bruce and me are working on a system that should give
us something better than 10ps (my guess is that we should get close
to 1ps) at a rate of (guestimated) 1MHz per channel. (Based on the
excitation of a LC tank and measuring the ring-down/phase with an ADC).
As it is with researches, we want the moon, and prossible even more.
So we were talking about getting the measurement rate up even higher,
to 10MHz and if possible 50MHz with the same precision. The above
approche will not work above 1MHz. Using different filters it might
be possible to get it up to maybe 10MHz, but it would be an awkward
design at best.
The only methods I am aware of (and could find) that achieve such high
rates are those, based on (vernier) delay lines (and their equivalent
ring oscillator ones) in ASICs. But this means that a costly ASIC needs
to be produced.
Does someone know of other methods that could achieve high measurements
rates with better than 10ps precision/accuracy? (This question is mostly
a hypothetical question out of interest, I don't plan to build one...yet :-)
Attila Kinali
Massive parallelism of a simple NUTT style interpolator (charge capacitor with
say 10mA, rundown with say 1uA, use 100MHz clock or faster clock ).
With a custom IC for the analog part, a resolution of 1ps should be feasible.
An FPGA can do all the non critical stuff like the rundown counting.
The problem is to ensure that the front end logic that selects the next non-
busy interpolator doesn't accumulate excessive jitter from cascaded gates.
The same issue of accumulated jitter produced by cascaded gates/inverters can
limit the performance of vernier delay line style interpolators. Minimising
the number of series inverters by using a higher frequency clock (100MHZ,
1GHz??) should help somewhat.
Bruce
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To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts
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