High rate, high precision/accuracy time interval counter methods
One method is to have the event trigger sampling of a pair of quadrature phase sinewaves. eg LT1407A-1 dual 14 bit SAR ADC can sample a quadrature pair of 10MHz sine waves with ~ 5ps resolution in the computed phase.
Bruce
On Wednesday, 4 May 2016 10:00 PM, Attila Kinali <attila@kinali.ch> wrote:
On Tue, 3 May 2016 22:31:14 +0200
Magnus Danielson magnus@rubidium.dyndns.org wrote:
An alternative to the edge estimator method is to continuously sample,
mix with a reference frequency, decimate and then do arc-tangent of the
I/Q samples. This is what is used for phase-noise measurement such as
the Symmetricom/Microsemi test-kits, TimePod, and also the new R&S
phase-noise system.
The "signal" is not a sinusoid, but discrete events. Think of it
as incomming pulses and you want to measure their arrival time.
Attila Kinali
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On 05/04/2016 10:38 AM, Attila Kinali wrote:
On Tue, 3 May 2016 22:31:14 +0200
Magnus Danielson magnus@rubidium.dyndns.org wrote:
An alternative to the edge estimator method is to continuously sample,
mix with a reference frequency, decimate and then do arc-tangent of the
I/Q samples. This is what is used for phase-noise measurement such as
the Symmetricom/Microsemi test-kits, TimePod, and also the new R&S
phase-noise system.
The "signal" is not a sinusoid, but discrete events. Think of it
as incomming pulses and you want to measure their arrival time.
Which cuts away that option, yes. Naturally. The mixdown variant assumes
a repeating pulse patter, but it does not assume sine.
Cheers,
Magnus
Am 04.05.2016 um 10:46 schrieb Bruce Griffiths:
Integrating A Time interval to charge TAC at the front end of a capacitive charge redistribution SAR ADC should allow a conversion time of 300ns or so.. Using 16 such TDCs should permit 1ps resolution with a 50MHz timestamp rate without too many cascaded gates in the selection logic for the next available TAC.
Bruce
One or two years ago I investigated a solution around a 16 Bit / 100
MSPS ADC (LTC2165), a 2C64 Coolrunner,
an Avago PHEMT as current switch and a little bit of analog voodoo. That
would have fit on a 2"*2" board.
Good enough for a 10 MHz event rate, with some easy pipelining for at
least 20 MHz.
That includes the coarse counter from the last 1pps.
But we stayed with a classical time stretcher, and my private project
pipeline is already full.
regards, Gerhard
Hi,
Indeed. ADC conversion speed is not a big issue these days, so the Nutt
style of interpolator is just expensive to parallelize for speed, the
time-to-voltage system is better and should have a much better
recycle-time and thus result in less hardware needs.
Cheers,
Magnus
On 05/04/2016 10:46 AM, Bruce Griffiths wrote:
Integrating A Time interval to charge TAC at the front end of a capacitive charge redistribution SAR ADC should allow a conversion time of 300ns or so.. Using 16 such TDCs should permit 1ps resolution with a 50MHz timestamp rate without too many cascaded gates in the selection logic for the next available TAC.
Bruce
On Wednesday, 4 May 2016 12:00 PM, Bruce Griffiths <bruce.griffiths@xtra.co.nz> wrote:
On Tuesday, May 03, 2016 02:31:17 PM Attila Kinali wrote:
Hi,
We had here a discussion about measuring events (ie time stamping
them precisely) with high rates. As some of you know, Javier and
his group, Bruce and me are working on a system that should give
us something better than 10ps (my guess is that we should get close
to 1ps) at a rate of (guestimated) 1MHz per channel. (Based on the
excitation of a LC tank and measuring the ring-down/phase with an ADC).
As it is with researches, we want the moon, and prossible even more.
So we were talking about getting the measurement rate up even higher,
to 10MHz and if possible 50MHz with the same precision. The above
approche will not work above 1MHz. Using different filters it might
be possible to get it up to maybe 10MHz, but it would be an awkward
design at best.
The only methods I am aware of (and could find) that achieve such high
rates are those, based on (vernier) delay lines (and their equivalent
ring oscillator ones) in ASICs. But this means that a costly ASIC needs
to be produced.
Does someone know of other methods that could achieve high measurements
rates with better than 10ps precision/accuracy? (This question is mostly
a hypothetical question out of interest, I don't plan to build one...yet :-)
Attila Kinali
Massive parallelism of a simple NUTT style interpolator (charge capacitor with
say 10mA, rundown with say 1uA, use 100MHz clock or faster clock ).
With a custom IC for the analog part, a resolution of 1ps should be feasible.
An FPGA can do all the non critical stuff like the rundown counting.
The problem is to ensure that the front end logic that selects the next non-
busy interpolator doesn't accumulate excessive jitter from cascaded gates.
The same issue of accumulated jitter produced by cascaded gates/inverters can
limit the performance of vernier delay line style interpolators. Minimising
the number of series inverters by using a higher frequency clock (100MHZ,
1GHz??) should help somewhat.
Bruce
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For the sensor timestamping you can try replicate an avalanche effect
with a device which uses a pn-pn substrate configuration ... or
something similar to the avalanche photodiodes.
The avalanche photodiode has very high gain and a response time of some
ps (5ps a commercial APD).
This system may cause some effects like high noise and would need high
breakdown voltages however.
The spurious capacitances can be minimized because in APDs it depends on
the sensor area, which is not needed in your case.
Regards,
Ilia.
On 05/03/16 12:31, Attila Kinali wrote:
Hi,
We had here a discussion about measuring events (ie time stamping
them precisely) with high rates. As some of you know, Javier and
his group, Bruce and me are working on a system that should give
us something better than 10ps (my guess is that we should get close
to 1ps) at a rate of (guestimated) 1MHz per channel. (Based on the
excitation of a LC tank and measuring the ring-down/phase with an ADC).
As it is with researches, we want the moon, and prossible even more.
So we were talking about getting the measurement rate up even higher,
to 10MHz and if possible 50MHz with the same precision. The above
approche will not work above 1MHz. Using different filters it might
be possible to get it up to maybe 10MHz, but it would be an awkward
design at best.
The only methods I am aware of (and could find) that achieve such high
rates are those, based on (vernier) delay lines (and their equivalent
ring oscillator ones) in ASICs. But this means that a costly ASIC needs
to be produced.
Does someone know of other methods that could achieve high measurements
rates with better than 10ps precision/accuracy? (This question is mostly
a hypothetical question out of interest, I don't plan to build one...yet :-)
Attila Kinali
--
Ilia Platone
via Ferrara 54
47841
Cattolica (RN), Italy
Cell +39 349 1075999
On Wednesday, May 04, 2016 02:22:22 PM Gerhard Hoffmann wrote:
Am 04.05.2016 um 10:46 schrieb Bruce Griffiths:
Integrating A Time interval to charge TAC at the front end of a capacitive
charge redistribution SAR ADC should allow a conversion time of 300ns or
so.. Using 16 such TDCs should permit 1ps resolution with a 50MHz
timestamp rate without too many cascaded gates in the selection logic for
the next available TAC. Bruce
One or two years ago I investigated a solution around a 16 Bit / 100
MSPS ADC (LTC2165), a 2C64 Coolrunner,
an Avago PHEMT as current switch and a little bit of analog voodoo. That
would have fit on a 2"*2" board.
Good enough for a 10 MHz event rate, with some easy pipelining for at
least 20 MHz.
That includes the coarse counter from the last 1pps.
But we stayed with a classical time stretcher, and my private project
pipeline is already full.
regards, Gerhard
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Yes, taking advantage of the fact that one merely uses the fine time interval
measurement to measure the delay of a synchroniser clocked with the same clock
as the ADC makes the design relatively simple. The output of the synchroniser
samples a counter clocked with the same clock as the ADC to produce the fine
count. The Time to amplitude converter output is merely held for 1 or 2 clock
cycles so the ADC can sample the relevant part of the output. The TAC output
is then reset to zero (or better the opposite limit of the ADC input). Either
a buffer is used between the TAC and ADC or a direct connection should be
feasible as long as the effect of sampling during ramping of the TaC output
(TAC output capacitor is being charged) is corrected for. That is correcting
for the charge transfer during this undesired sample. The sample taken when
the TAC is in hold being corrected for the charge transfer incurred by the
sample taken during ramping. Alternatively the TAC current could be used to
drrive a network with a suitable impulse response so that no explicit reset is
required. The output of this network being sampled by the ADC. The fine time
interval can then be recovered by curve fitting to the samples taken by the
ADC.
Bruce
Am 05.05.2016 um 01:55 schrieb Bruce Griffiths:
On Wednesday, May 04, 2016 02:22:22 PM Gerhard Hoffmann wrote:
But we stayed with a classical time stretcher, and my private project
pipeline is already full.
Talking about my own pipeline:
I have finally ordered today the first 20 samples of my OCXO carrier
board for
OCXOs that can be locked to an external ref, 1pps out, optional doubler
etc...
It can also be a home for Tom's picDIV.
I just imagine a gang of 16 MTI-260s, each slooowly locked to an
external ref
with their outputs wilkinsoned together to make a make a really low phase
noise 10 MHz source. I have bought a pretty number of those Lucent 24386
units without GPS for their MTis. :-) I mean, we cannot get those
BVAs anymore.
Screen dump of the Board:
http://www.hoffmann-hochfrequenz.de/downloads/ocxo_carrier_screendump.png
Sorry for the red/green blind.
regards, Gerhard
Gerhard wrote:
I just imagine a gang of 16 MTI-260s, each slooowly locked to an
external ref with their outputs wilkinsoned together to make a
make a really low phase noise 10 MHz source. I have bought a
pretty number of those Lucent 24386 units without GPS for their
MTis. :-) I mean, we cannot get those BVAs anymore.
regards, Gerhard
I have been thinking along the same lines, to combine multiple OCXOS's to
obtain lower phase noise. But an N-way Wilkinson could get tedious. After
you calculate the impedances for each leg, you then have to convert them to
lumped-element equivalents to run at 10 MHz, as shown here:
http://www.microwaves101.com/encyclopedias/lumped-element-wilkinson-splitters
The contribution from each OCXO may not be perfectly balanced, and it may
be difficult to calculate the relative contribution of each, especially
when you consider component tolerances. The isolation between units can be
fairly low; perhaps -13dB to -20dB. This could have serious effects when
running into a PLL. The Wilkson is a relatively narrow-band device and
could not be used for other oscillator banks at considerably different
frequencies.
I propose using a simple resistive combiner. The loss is -6dB, which can
easily be made up in the distribution amplifier. The balance is as perfect
as the resistor tolerances you use. Depending on how you model the OCXO
output stage, the isolation can be better than -40dB from a single unit.
I am attaching LTspice files to show the loss from each oscillator to the
output, and the isolation between oscillators. I used 10 units to help a
little in mental calculations for sanity checking.
The noise contribution is determined by the resistor network. In this
example, it is 5 Ohms in parallel with 5 ohms, or 2.5 ohms. The
contribution of the combiner is then negligible. A resistive combiner is
inherently broadband, and could easily be used over a 100:1 frequency range
with a little care in construction.
I think isolation is the main deal. When you have a bank of oscillators at
the same frequency feeding a pll that is supposed to respond to only one,
the effect of the other units could be significant. It may be necessary to
further isolate the units by providing separate outputs to feed the pll and
the combiner.
But in principle, I think it is a very good idea.
Mike
Hi
Be careful of isolation specs on some of these combiners / splitters. Often they are deponent on the return loss
of the signal source. An OCXO that presets a 12 db return loss is doing ok. One that is past 20 db is doing quite well.
Bob
On May 5, 2016, at 7:00 PM, Mike Monett timenuts@binsamp.e4ward.com wrote:
Gerhard wrote:
I just imagine a gang of 16 MTI-260s, each slooowly locked to an
external ref with their outputs wilkinsoned together to make a
make a really low phase noise 10 MHz source. I have bought a
pretty number of those Lucent 24386 units without GPS for their
MTis. :-) I mean, we cannot get those BVAs anymore.
regards, Gerhard
I have been thinking along the same lines, to combine multiple OCXOS's to
obtain lower phase noise. But an N-way Wilkinson could get tedious. After
you calculate the impedances for each leg, you then have to convert them to
lumped-element equivalents to run at 10 MHz, as shown here:
http://www.microwaves101.com/encyclopedias/lumped-element-wilkinson-splitters
The contribution from each OCXO may not be perfectly balanced, and it may
be difficult to calculate the relative contribution of each, especially
when you consider component tolerances. The isolation between units can be
fairly low; perhaps -13dB to -20dB. This could have serious effects when
running into a PLL. The Wilkson is a relatively narrow-band device and
could not be used for other oscillator banks at considerably different
frequencies.
I propose using a simple resistive combiner. The loss is -6dB, which can
easily be made up in the distribution amplifier. The balance is as perfect
as the resistor tolerances you use. Depending on how you model the OCXO
output stage, the isolation can be better than -40dB from a single unit.
I am attaching LTspice files to show the loss from each oscillator to the
output, and the isolation between oscillators. I used 10 units to help a
little in mental calculations for sanity checking.
The noise contribution is determined by the resistor network. In this
example, it is 5 Ohms in parallel with 5 ohms, or 2.5 ohms. The
contribution of the combiner is then negligible. A resistive combiner is
inherently broadband, and could easily be used over a 100:1 frequency range
with a little care in construction.
I think isolation is the main deal. When you have a bank of oscillators at
the same frequency feeding a pll that is supposed to respond to only one,
the effect of the other units could be significant. It may be necessary to
further isolate the units by providing separate outputs to feed the pll and
the combiner.
But in principle, I think it is a very good idea.
Mike
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Am 06.05.2016 um 01:00 schrieb Mike Monett:
I have been thinking along the same lines, to combine multiple OCXOS's to
obtain lower phase noise. But an N-way Wilkinson could get tedious. After
you calculate the impedances for each leg, you then have to convert them to
lumped-element equivalents to run at 10 MHz, as shown here:
NoNoNo, you can build a replacement with a 1:1 balun transformer and a
100 Ohms resistor.
With a little bit of ferrite this is both broadband and small.
It presents a 25 Ohms input resistance in a 50 Ohm system, so you need
another wideband
transformer with a 2/3 windings ratio. The resulting 4/9 impedance ratio
is close enough
to provide the impedance match from 25 to the 50 Ohm source.
That's probably what's inside a MiniCircuits PSC2-1. I have never opened
one but I don't
have much doubt.
They also have solutions for 8:1 and 16:1, but it can be cheaper d.i.y..
Someone in the US is currently selling 10 PSC2-1 on ebay IIRC. But for
me being in Europe the
transport would probably cost more than what it's worth.
regards, Gerhard