High rate, high precision/accuracy time interval counter methods
On Wed, 4 May 2016 15:26:37 +0200
Magnus Danielson magnus@rubidium.dyndns.org wrote:
Indeed. ADC conversion speed is not a big issue these days, so the Nutt
style of interpolator is just expensive to parallelize for speed, the
time-to-voltage system is better and should have a much better
recycle-time and thus result in less hardware needs.
True and not true. Yes, there are many ADCs that do high conversion
rates, but these are optimized for piplined applications where conversion
happens at a constant rate. Ie they expect a constant conversion clock
with a constant rate. If you want to trigger conversion at an arbitrary time,
you either have to build your own sampler or need to use one of the
non-pipelined ADCs whic are much slower (IIRC they stop around 5-10Msps
aka >100ns conversion time). Flash ADCs with direct access to the sampling
circuitry are basically extinct.
Attila Kinali
--
Reading can seriously damage your ignorance.
-- unknown
Am 08.05.2016 um 21:53 schrieb Attila Kinali:
True and not true. Yes, there are many ADCs that do high conversion
rates, but these are optimized for piplined applications where conversion
happens at a constant rate. Ie they expect a constant conversion clock
with a constant rate. If you want to trigger conversion at an arbitrary time,
you either have to build your own sampler or need to use one of the
non-pipelined ADCs whic are much slower (IIRC they stop around 5-10Msps
aka >100ns conversion time). Flash ADCs with direct access to the sampling
circuitry are basically extinct.
You can run the ADC on constant 100 MHz for example. The charged
capacitor has to wait an
extra 0 to 10 ns until it is read out. That is easy. In a time
stretcher you must keep the charge and
discharge it in a controlled way in 50 usec, and over that time, bias
currents etc really
do play a role.
regards, Gerhard
Am 08.05.2016 um 21:53 schrieb Attila Kinali:
...
Maybe I was too short. We have control over the charging current source,
and when we switch it off, the status quo is kept. Then when the ADC is
done,
we can simply short the capacitor in the next clock/s to prepare for the
next cycle.
Attilla, we could discuss that on a sunny evening in Saarbrücken in a
beer garden if you like. The season starts :-)
regards, Gerhard
Hi
On May 8, 2016, at 7:08 PM, Gerhard Hoffmann dk4xp@arcor.de wrote:
Am 08.05.2016 um 21:53 schrieb Attila Kinali:
...
Maybe I was too short. We have control over the charging current source,
and when we switch it off, the status quo is kept. Then when the ADC is done,
we can simply short the capacitor in the next clock/s to prepare for the next cycle.
Attilla, we could discuss that on a sunny evening in Saarbrücken in a
beer garden if you like. The season starts :-)
… but how about the rest of us :)
Bob
regards, Gerhard
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Yes, just a synchroniser clocked with the same clock as the ADC.The interpolator measures the synchroniser delay by charging the capacitor in the interval between the occurrence of the transition to be time stamped and when the output of the synchroniser recognises this transition.The ADC samples the capacitor voltage on the next clock.In reality the ADC samples its input continuously and the relevant sample is flagged by the synchroniser and associated logic.
Buffering the capacitor voltage avoids the need to correct for the effect of sampling the capacitor voltage during runup.However the buffer isn't essential as long as the correction is made and the ADC input is essentially capacitive.The ramp capacitor should be somewhat larger than the ADC input capacitance.
Bruce
On Monday, 9 May 2016 12:01 PM, Gerhard Hoffmann <dk4xp@arcor.de> wrote:
Am 08.05.2016 um 21:53 schrieb Attila Kinali:
....
Maybe I was too short. We have control over the charging current source,
and when we switch it off, the status quo is kept. Then when the ADC is
done,
we can simply short the capacitor in the next clock/s to prepare for the
next cycle.
Attilla, we could discuss that on a sunny evening in Saarbrücken in a
beer garden if you like. The season starts :-)
regards, Gerhard
time-nuts mailing list -- time-nuts@febo.com
To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts
and follow the instructions there.
On Sun, 8 May 2016 21:53:56 +0200, you wrote:
On Wed, 4 May 2016 15:26:37 +0200
Magnus Danielson magnus@rubidium.dyndns.org wrote:
Indeed. ADC conversion speed is not a big issue these days, so the Nutt
style of interpolator is just expensive to parallelize for speed, the
time-to-voltage system is better and should have a much better
recycle-time and thus result in less hardware needs.
True and not true. Yes, there are many ADCs that do high conversion
rates, but these are optimized for piplined applications where conversion
happens at a constant rate. Ie they expect a constant conversion clock
with a constant rate. If you want to trigger conversion at an arbitrary time,
you either have to build your own sampler or need to use one of the
non-pipelined ADCs whic are much slower (IIRC they stop around 5-10Msps
aka >100ns conversion time). Flash ADCs with direct access to the sampling
circuitry are basically extinct.
Attila Kinali
An integrating time to voltage converter effectively is an external
sample and hold so pipelined analog to digital converters are not a
problem except in complexity dealing with their latency.
Huh, Flash ADCs really are almost gone now and I did not even notice.
TI still has some available.
I wonder what the fastest SAR ADCs are now. Linear Technology is up
to 18 bits and 15 Msps in the same device but if it was the only
option, then its cost would convince me to consider alternative
designs.
How much will dielectric absorption in the capacitor affect the
accuracy of the result with such a high conversion rate? I am used to
dealing with it on much longer time scales and higher resolutions.
On Mon, 9 May 2016 01:08:05 +0200, you wrote:
Am 08.05.2016 um 21:53 schrieb Attila Kinali:
...
Maybe I was too short. We have control over the charging current source,
and when we switch it off, the status quo is kept. Then when the ADC is
done,
we can simply short the capacitor in the next clock/s to prepare for the
next cycle.
Attilla, we could discuss that on a sunny evening in Saarbrücken in a
beer garden if you like. The season starts :-)
regards, Gerhard
time-nuts mailing list -- time-nuts@febo.com
To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts
and follow the instructions there.
Another option is to use a low pass filter to increase the transition times of the signal to be timestamped and use a pipelined ADC to sample the filter output.Perhaps something like the attached filter derived from:
http://bears.ucsb.edu/rad/pubs/conference/MTT_S_2004.pdf
May be effective in that it has near Gaussian response with relatively low out of band SWR.
Bruce
On Monday, 9 May 2016 3:01 PM, David <davidwhess@gmail.com> wrote:
How much will dielectric absorption in the capacitor affect the
accuracy of the result with such a high conversion rate? I am used to
dealing with it on much longer time scales and higher resolutions.
On Mon, 9 May 2016 01:08:05 +0200, you wrote:
Am 08.05.2016 um 21:53 schrieb Attila Kinali:
...
Maybe I was too short. We have control over the charging current source,
and when we switch it off, the status quo is kept. Then when the ADC is
done,
we can simply short the capacitor in the next clock/s to prepare for the
next cycle.
Attilla, we could discuss that on a sunny evening in Saarbrücken in a
beer garden if you like. The season starts :-)
regards, Gerhard
time-nuts mailing list -- time-nuts@febo.com
To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts
and follow the instructions there.
time-nuts mailing list -- time-nuts@febo.com
To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts
and follow the instructions there.
Sure, and then we are back to a transition midpoint timing TDC. Or AC
couple it for a centroid timing TDC. These require a lot more
processing to generate a result compared to a time to amplitude
converter but with economical FPGAs and ARM microcontrollers, maybe
this does not matter.
I was just wondering about the speed limitations of a time to
amplitude based TDC. I am more comfortable with analog design than
using FPGAs.
On Mon, 9 May 2016 03:35:46 +0000 (UTC), you wrote:
Another option is to use a low pass filter to increase the transition times of the signal to be timestamped and use a pipelined ADC to sample the filter output.Perhaps something like the attached filter derived from:
http://bears.ucsb.edu/rad/pubs/conference/MTT_S_2004.pdf
May be effective in that it has near Gaussian response with relatively low out of band SWR.
Bruce
On Monday, 9 May 2016 3:01 PM, David davidwhess@gmail.com wrote:
How much will dielectric absorption in the capacitor affect the
accuracy of the result with such a high conversion rate? I am used to
dealing with it on much longer time scales and higher resolutions.
Hi,
On 05/08/2016 09:53 PM, Attila Kinali wrote:
On Wed, 4 May 2016 15:26:37 +0200
Magnus Danielson magnus@rubidium.dyndns.org wrote:
Indeed. ADC conversion speed is not a big issue these days, so the Nutt
style of interpolator is just expensive to parallelize for speed, the
time-to-voltage system is better and should have a much better
recycle-time and thus result in less hardware needs.
True and not true. Yes, there are many ADCs that do high conversion
rates, but these are optimized for piplined applications where conversion
happens at a constant rate. Ie they expect a constant conversion clock
with a constant rate. If you want to trigger conversion at an arbitrary time,
you either have to build your own sampler or need to use one of the
non-pipelined ADCs whic are much slower (IIRC they stop around 5-10Msps
aka >100ns conversion time). Flash ADCs with direct access to the sampling
circuitry are basically extinct.
You can let the ADC convert as a continuous process as long as you
filter out the samples you are interested in.
Cheers,
Magnus