Building a high resolution DAC
Hi,
I have been pondering how to build a high resolution DAC over the weekend.
Something like [1] but has the disadvantage of needing a pair of resistors
that have a 1:2^16 ratio. The 1M/15.4R is kind of unwieldy.
Fidling around a bit, I came to the conclusion that using an R-100R ladder
with 4 10bit PWM DACs would be a good solution. 100R and 10k resistors
are readily available in 0.1% 25ppm/°C (and actually quite cheap).
While the first stage gives 10bits, each additional stage gives
approximately another 7bits, resulting in a total of 29bits resolution.
The 3 remaining bits per stage can be used to linearize the whole
circuit.
Now this is where the problem starts. How do I measure the circuitry
to build a linearization table? The linearity error is dominated by
the first stage error which is in the order of 0.1% and thus 10bits.
It would be necessary to measure this to somewhere close to 29bits, but
the best DACs that are readily available are 24bit. Yes, there is the
possibility to build some ADC that could do 28bit, but I am not exactly
keen on building something aking an HP3458 (mostly to avoid the
embarrasment of failing at doing so).
So, the question is how would one calibrate something like this?
Or am I missing something fundamental here?
Thanks in advance
Attila Kinali
[1] "DC-accurate 32-bit DAC achieves 32-bit resolution",
by Stephen Woodward, 2008
--
It is upon moral qualities that a society is ultimately founded. All
the prosperity and technological sophistication in the world is of no
use without that foundation.
-- Miss Matheson, The Diamond Age, Neil Stephenson
Best to ask volt-nuts?
On Mon, Aug 17, 2015 at 3:16 PM, Attila Kinali attila@kinali.ch wrote:
Hi,
I have been pondering how to build a high resolution DAC over the weekend.
Something like [1] but has the disadvantage of needing a pair of resistors
that have a 1:2^16 ratio. The 1M/15.4R is kind of unwieldy.
Fidling around a bit, I came to the conclusion that using an R-100R ladder
with 4 10bit PWM DACs would be a good solution. 100R and 10k resistors
are readily available in 0.1% 25ppm/°C (and actually quite cheap).
While the first stage gives 10bits, each additional stage gives
approximately another 7bits, resulting in a total of 29bits resolution.
The 3 remaining bits per stage can be used to linearize the whole
circuit.
Now this is where the problem starts. How do I measure the circuitry
to build a linearization table? The linearity error is dominated by
the first stage error which is in the order of 0.1% and thus 10bits.
It would be necessary to measure this to somewhere close to 29bits, but
the best DACs that are readily available are 24bit. Yes, there is the
possibility to build some ADC that could do 28bit, but I am not exactly
keen on building something aking an HP3458 (mostly to avoid the
embarrasment of failing at doing so).
So, the question is how would one calibrate something like this?
Or am I missing something fundamental here?
Thanks in advance
Attila Kinali
[1] "DC-accurate 32-bit DAC achieves 32-bit resolution",
by Stephen Woodward, 2008
--
It is upon moral qualities that a society is ultimately founded. All
the prosperity and technological sophistication in the world is of no
use without that foundation.
-- Miss Matheson, The Diamond Age, Neil Stephenson
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On Mon, 17 Aug 2015 15:28:10 +0200
Azelio Boriani azelio.boriani@gmail.com wrote:
Best to ask volt-nuts?
I thought this was volt-nuts? ;-)
Attila Kinali
--
It is upon moral qualities that a society is ultimately founded. All
the prosperity and technological sophistication in the world is of no
use without that foundation.
-- Miss Matheson, The Diamond Age, Neil Stephenson
On Mon, 17 Aug 2015 15:16:05 +0200
Attila Kinali attila@kinali.ch wrote:
I have been pondering how to build a high resolution DAC over the weekend.
Something like [1] but has the disadvantage of needing a pair of resistors
that have a 1:2^16 ratio. The 1M/15.4R is kind of unwieldy.
Fidling around a bit, I came to the conclusion that using an R-100R ladder
with 4 10bit PWM DACs would be a good solution. 100R and 10k resistors
are readily available in 0.1% 25ppm/°C (and actually quite cheap).
While the first stage gives 10bits, each additional stage gives
approximately another 7bits, resulting in a total of 29bits resolution.
The 3 remaining bits per stage can be used to linearize the whole
circuit.
Maybe a small clarification here:
The goal is to build a DAC with 26bit resolution and small DNL.
INL is not the critical value, but the output should be kind of stable.
But given how reality looks like, i would already be happy with 24bit and
would accept something >20bits as well. (For 20bit there are decent
chips at cheap prices available)
Attila Kinali
--
It is upon moral qualities that a society is ultimately founded. All
the prosperity and technological sophistication in the world is of no
use without that foundation.
-- Miss Matheson, The Diamond Age, Neil Stephenson
Em 17/08/2015 10:16, Attila Kinali escreveu:
So, the question is how would one calibrate something like this?
Or am I missing something fundamental here?
If tasked with such mission i would pick a 7.5 digits meter, connect the
DAC to it, connect both to a computer, excite every code of the DAC and
log the output from the meter. Then i would plot and figure a way to
compress the table (linearize the output). Probably some temp
compensation would play here too... so it must be done with the dac in
different temperatures.
Daniel
In message 20150817151605.6b4150803df29771b9b95ec9@kinali.ch, Attila Kinali w
rites:
I have been pondering how to build a high resolution DAC over the weekend.
I've been looking at the same thing occationally, but every time I
do the math I reach the conclusion that once you get past 18-20
bits things get really icky.
I don't see any realistic way to directly go beyond 24 bits which
isn't based on time division rather than unobtainium calibrated
artifacts (resistors/capacitors). (Read HP's article about the
kelvin-varley-divider they built from calibration-quality resistors...)
On the other hand, it's perfectly possible to get cheap-ish 32 bit
ADCs, which do a pretty good job of not making you laugh.
That points to a hybrid scheme.
Something like 3 twelve-bit DACs cascaded with plenty of overlap,
sampled by a 32 bit ADC, and connected to a sample&hold.
Once the desired value is obtained, switch to sample mode.
As long as you only need slow incremental response from there, you can
leave the Sample&Hold sampling all the time.
Once you get to the end of the lowest DACs range, you need to switch
to Hold until you have your DAC(-lings) into a row again.
I have not tried this yet myself, but once I get down through my
pile of more important projects, but I'll be happy to lend any
assistance I can to the project.
--
Poul-Henning Kamp | UNIX since Zilog Zeus 3.20
phk@FreeBSD.ORG | TCP/IP since RFC 956
FreeBSD committer | BSD since 4.3-tahoe
Never attribute to malice what can adequately be explained by incompetence.
On Mon, 17 Aug 2015 10:47:15 -0300
Daniel Mendes dmendesf@gmail.com wrote:
If tasked with such mission i would pick a 7.5 digits meter, connect the
7 digits is just about 23/24bits. An on-board 24bit ADC can do that
as well (with carefull design, of course)
DAC to it, connect both to a computer, excite every code of the DAC and
log the output from the meter.
If possible, i don't want to use an external device for calibration.
Because an internal calibrator would allow to recalibrate the system
from time to time, without the need to run to a calibration lab.
The absolute calibration is not important (the DAC is part of a control
loop), but that DNL is low and stable in the range of hours to days.
Small drift is not a problem either (again, control loop) as long
as the DNL stays within limits.
Then i would plot and figure a way to compress the table (linearize the output).
Compression is easy: there are 4 PWM DACs, which are inherently linear.
Ie it's enough to express the slope of each of those PWM DACs by a number.
Probably some temp
compensation would play here too... so it must be done with the dac in
different temperatures.
That's the next thing. But I will not worry about tempco until
the fundamental problem is solved :-)
Attila Kinali
--
It is upon moral qualities that a society is ultimately founded. All
the prosperity and technological sophistication in the world is of no
use without that foundation.
-- Miss Matheson, The Diamond Age, Neil Stephenson
On Mon, 17 Aug 2015 14:15:53 +0000
"Poul-Henning Kamp" phk@phk.freebsd.dk wrote:
I have been pondering how to build a high resolution DAC over the weekend.
I've been looking at the same thing occationally, but every time I
do the math I reach the conclusion that once you get past 18-20
bits things get really icky.
Yes, I came to the same conclusion. Well 20bit at 5V span already
means an LSB of ~4uV, which is already close to the limit what
average opamps can do on noise performance. 24bit are 300nV
which means that anything using this voltage needs to do
some internal avaraging/integration...
I don't see any realistic way to directly go beyond 24 bits which
isn't based on time division rather than unobtainium calibrated
artifacts (resistors/capacitors). (Read HP's article about the
kelvin-varley-divider they built from calibration-quality resistors...)
On the other hand, it's perfectly possible to get cheap-ish 32 bit
ADCs, which do a pretty good job of not making you laugh.
That points to a hybrid scheme.
You mean the AD7177-2? That seems to be quite hard to get by.
And those who have it, want around 50USD for it.
My goal was to stay below 30-40USD for the whole DAC if possible.
But yes.. it might not be possible.
I have not tried this yet myself, but once I get down through my
pile of more important projects, but I'll be happy to lend any
assistance I can to the project.
Thanks for the offer! That would be really cool.
The whole project is already getting too big for me.
And new problems are popping up left and right...
Attila Kinali
--
It is upon moral qualities that a society is ultimately founded. All
the prosperity and technological sophistication in the world is of no
use without that foundation.
-- Miss Matheson, The Diamond Age, Neil Stephenson
Hello,
see my comments on the cirquit [1] here:
https://www.febo.com/pipermail/volt-nuts/2010-October/000537.html
So it will get very hard to go below 1ppm linearity. (without a
exact/calibrated feedback loop).
Since the formula in the article is wrong you will need some overlapping
bits anyway.
With best regards
Andreas
Am 17.08.2015 um 15:16 schrieb Attila Kinali:
Hi,
I have been pondering how to build a high resolution DAC over the weekend.
Something like [1] but has the disadvantage of needing a pair of resistors
that have a 1:2^16 ratio. The 1M/15.4R is kind of unwieldy.
Fidling around a bit, I came to the conclusion that using an R-100R ladder
with 4 10bit PWM DACs would be a good solution. 100R and 10k resistors
are readily available in 0.1% 25ppm/°C (and actually quite cheap).
While the first stage gives 10bits, each additional stage gives
approximately another 7bits, resulting in a total of 29bits resolution.
The 3 remaining bits per stage can be used to linearize the whole
circuit.
Now this is where the problem starts. How do I measure the circuitry
to build a linearization table? The linearity error is dominated by
the first stage error which is in the order of 0.1% and thus 10bits.
It would be necessary to measure this to somewhere close to 29bits, but
the best DACs that are readily available are 24bit. Yes, there is the
possibility to build some ADC that could do 28bit, but I am not exactly
keen on building something aking an HP3458 (mostly to avoid the
embarrasment of failing at doing so).
So, the question is how would one calibrate something like this?
Or am I missing something fundamental here?
Thanks in advance
Attila Kinali
[1] "DC-accurate 32-bit DAC achieves 32-bit resolution",
by Stephen Woodward, 2008
In message 20150817162946.93e5cee64c9c8a820c6a0e03@kinali.ch, Attila Kinali w
rites:
You mean the AD7177-2? That seems to be quite hard to get by.
I was thinking of the TI part intended for seismic applications.
My goal was to stay below 30-40USD for the whole DAC if possible.
But yes.. it might not be possible.
I don't think it is. The necessary voltage reference will set you
back almost that much...
--
Poul-Henning Kamp | UNIX since Zilog Zeus 3.20
phk@FreeBSD.ORG | TCP/IP since RFC 956
FreeBSD committer | BSD since 4.3-tahoe
Never attribute to malice what can adequately be explained by incompetence.