On April, 24th Ulrich Bangert wrote:

I have built the cirquit from EDN (with some modifications) which seems to
be the same that Ulrich used:
http://www.edn.com/article/471981-DC_accurate_32_bit_DAC_achieves_32_bit_resolution.php

but the values that are stated in the article are far beyond that what I
have measured.

My modifications are: using MAX6250A instead of AD586L.
R2,R3 = 51R and R6 = 0R so that I get around 30 Bits resolution with 2 Bits
overlap.
C1 = 100nF , R1 = 100K with 100 Hz period. (I tried 244 Hz period with R1 =
41K but this has nearly no impact)
All built on a soldered breadboard using star grounding.

The issues that I have with the cirquit are:

1. the given formula for output voltage is not correct. When recalculating I
   get 50% from VRef at PWMH = 8000 and PWML = 8000 since the voltages are not
   added. They are mixed in relation to the resistor values. The maximum output
   voltage one can get is 65535/65536 * VRef.

2. Linearity: With the original 5 Ohms Resistor I measured around 60-65uV
   maximum linearity deviation at 2.5V Output. This would give about 16 Bits
   Linearity in my case. Carefully adjusting R7 to linearity (7.18 Ohms) gives
   around 12-15uV (3ppm) linearity. But this is far from the 22 bits = 0.3 ppm
   linearity stated in the article. The linearity curve is relative flat up to
   75-80% of the range. Above 80% the linearity error increases continously.

3. settling time: Although having carefully adapted the integration time
   constant to the period time the output gets only 80-90% of the voltage step
   in the first step. When looking at the oscilloscope the integrator output
   breakes down at the time when S3 switches. So it needs around 5 PWM cycles
   to settle on the scope.

4. Large current spikes through S3: At 2.5V Output the integration capacitor
   will have 2.5Vpp Integration ripple. When having a 50% duty cycle for S3
   there will be current spikes of 2.5V limited only by the 200R resistor and
   the resistance of the switch. These spikes increase the output noise. (I
   measured around 100uVpp with a LTC2400 A/D-Converter). Increasing the PWM
   duty cycle to around 97% will give a good compromize between noise and
   settling time of the output capacitors.

5. large negative output spikes on voltage steps >= around 0.5V: When
   switching between 2 PWM duty cycle values I see large negative spikes (up to
   negative voltages) on the output voltage. For me it seems that the input
   protection diodes between negative and positive input (1.1V forward voltage)
   are going to be forward biased.

6. Output noise measured with a bandwidth limited fourth order (0.1Hz to 10
   Hz) amplifier (10000 fold) shows 10-15uVpp "noise". This noise is not
   randomly distributed but shows some cyclical staircased behaviour.
   The 100nF capacitor for the first integrator is a polypropylene type. The
   two 1uF capacitors are still mylar type. Perhaps the "staircase" has
   something to do with dielectric absorption.

Has anybody any idea how to get better results from this cirquit? Anyone
else who built this cirquit?

@Ulrich: how did you get your good results from noise measuring (only the
LTZ1021 noise = 3uVpp)
Which capacitor types did you use? mylar or polypropylene or else?
Any hints on the building of the cirquit?

best regards

Andreas

Hello Andreas,

when I came over this circuit I was in search for a 24 Bit DAC for the EFC
of an OCXO. For hat reason everything was a bit less ambitious than you are
in search for. The reference I used was a LT1021, much inferior than the
LTZ1000 in terms of tempco but no problem for this application because its
use inside a closed regulation loop. The resistor networks were computed
new, so i have no experience with it's original values.

The noise measurements that I made were done with a HP3457 in
"high-resolution" mode (7-1/2 digits). The HP3457 was set to integrate over
50 power line cycles. If I remember correct the noise that i measured was
pretty much that of the reference divided down according to the pwm ratio.

Best regards
Ulrich Bangert

Andreas

There is an large error in the resistor values that determine the gain
of the LS PWM DAC in the EDN article resulting in a gain mismatch
between the most significant 16 bit PWM DAC and the least significant
PWM DAC.
The resultant linearity error is much larger than the effect of the
difference between the 5 ohms and the 7.15 ohms you used.
This gain mismatch will result in the ~ 16 bit nonlinearity error that
you observed.

Bruce

Ulrich Bangert wrote:

Andreas

Incorrect, the output of the error integrator is (or should be) sampled
when its output is small except during the first cycle after a large
step change in the MS PWM duty cycle.
Thus the current transients in the sampling capacitor and switch should
be relatively small once the circuit has settled.

If the difference in output corresponding to the 2 PWM values is small
as is almost always the case when the DAC is used to set the EFC voltage
of the OCXO in a GPSDO or similar control loop such behaviour shouldn't
be an issue.

Dielectric absorption will increase the settling time but shouldnt
produce staircase effects.
However, Mylar has significant dielectric absorption.

Bruce

Hello,

so I guess that you measured the effective (rms) voltage noise in the AC
range of the HP3457?
And this as broadband measurement (>= 1 MHz bandwidth of the HP) ?

Whereas I measured the 0.1 .. 10Hz  uVpp noise with an Oscilloscope.
If this is true the two values cannot be compared.

Best regards

Andreas

Hello Bruce,

How do you think that the resistor values should be?

When calculating from the diagram 15.4 Ohms * 65536 = 1009254.4 Ohm
which comes close to the serial resistance of the 1Meg + 9K2 + RDS,on of the
MAX4053.
the other of the 1Meg is shorted always either to Gnd or to the reference.
Or am I wrong ?

http://www.edn.com/article/471981-DC_accurate_32_bit_DAC_achieves_32_bit_resolution.php

In my linearity measurements I always used the same values for the high and
low PWM-Value.
So I think that the gain mismatch should cancel out in this special case.

When I have correctly understood the 5 Ohms should cancel out the RDS,on for
the switch S1
which is higher when the voltage across the switch is near +5V and lower
when the voltage
is near 0V. The RDS,on (high and low) and R7 are in series to the
integration resistor R1 (88K7)
so each Ohm mismatch will result in around 6 ppm error at 50% duty cycle.
Unfortunately the RDS,on is not temperature independent.

With best regards

Andreas

Andreas

Andreas Jahn wrote:

I will answer in more detail tonight (my time when I dig up my analysis
notes on this) and include an analysis of acquisition transient currents
in the 1uF sampling capacitor as a function of MS PWM duty cycle, etc.

The Thevinen equivalent source  at pin 15 of the MAX4053A has a series
resistance of  0.5M + 9K2 connected to 2.5V.
The 9K2 resistor should actually have a value of 4K6.

How do you make linearity measurements with both the MS and LS PWM
values fixed?
Surely you mean that you kept the LS PWM value fixed whilst varying the
MS PWM value?

Your comments on forward biasing the analog switch protection diodes are
somewhat perplexing as the analog switch negative supply (Vee) should be
-5V.
1.5V transients are well within the resultant +5V to -5V range for which
the analog switch protection diodes are reverse biased.

Unless of course you connected the analog switch Vee to GND.

The circuit should also work with an HC4053 substituted for the MAX4053.

Bruce

Hello Bruce,

voltage):
Initially the output integrator is zero. During the first 50% the error
integrator ramps towards -2,5V.
when switching the switched capacitor to the error integrator at 50% it will
be charged to around -2,5V.
On switching back at the end of the period the switched capacitor is
discharged to the output Integrator
giving near +2,5V.
When reaching steady state I see the following:
The error integrator starts from 0 Volts and ramps down to -1,25V during the
first 50% of the Duty cycle.
(Difference of  5V-2,5V integrated for 50% time). During 50-100% of the duty
cycle the voltage ramps back to 0V.
When having S3 at 50% Duty cycle the switched capacitor is charged quickly
to -1.25V and ramped back
till 100% of the period. Across the 200 Ohms resistor I see a negative
voltage spike of around 900-1000mV
giving a peak current of around -5mA across the switch.

So if I have understood you right your suggestion is to change the PWM for
the switched capacitor
at the first cycle to around the same value as the High PWM and after this
back to a value where the
error integrator is near zero (this will be near 100%).

You are right: practically this has nearly no impact. Except when the stage
that follows will
be disturbed by negative voltages one should divide large output steps into
a couple of smaller steps.

With best regards.

Andreas

What I am actually doing is the following:
I put the PWMH = 0x8000 and PWML = 0x8000. As output I expect exactly 50% of
the reference voltage.
(I know the formula in the article would expect 50% at PWMH = 0x8000 and
PWML = 0x0000
but the formula in the article is wrong as you can easyly check at 0xFFFF
for both outputs).
I measure the reference voltage (e.g. 4999.056mV) and the output voltage
(e.g. 2499.463 mV) with my LTC2400 ADC (integrating all measurements over 1
minute to get the noise below 1 .. 2 uV)
I would expect  2499.528 mV so the error is -65uV.
I will do this for all steps PWMH = PWML =  0x0000, 0x1000, 0x2000, ....
0xF000, 0xFFFF (or even finer resolution).
I will get e.g. -2 uV at 0x0000 and -8 uV at 0xFFFF and -47 uV at 0x4000.
The largest deviation from the expected value gives the maximum INL-error.

Perhaps I wrote not clearly enough:
The LTC1151 seems to have some protection diodes
between the positive and the negative inputs of the amplifier.
At least I can measure around 1,1 to 1,2V in each direction
in diode testing of my multimeter between the two inputs.
Which would give two diodes in series in each direction.
Since there are no series resistors on most of the inputs
some unwanted current paths exist in the cirquit on large transients.

I have tried this (the MAX4053 is not really cheap).
my results: (all before tweaking linearity).

HCF4053 (=CD4053)  +100uV to -200 uV linearity error.
74HCT4053                  +0 to  -600 uV linearity error!!!! (I did not
expect this)
MAX4053A                  +0 to  -65 uV linearity error

I did not check the root cause of the error and why the HCT has more error
than the HCF.
(Leakage current, charge transfer, RDS,on span or switching times + break
before make tolerance).
The MAX4053A is specified much better in all parameters. And in this
application
he has the best linearity of the 3 tested multiplexer samples.

With best regards

Andreas

Andreas Jahn wrote:

Not really you should fit a straight line to the results first.
The INL is then the given by the largest deviation from this straight line.

A very clean board with low leakage from the supplies to the opamp
inputs together with shielding from air currents are necessary for low
noise.
Changing thermoemfs due to fluctuating temperature differences and
circuit board leakage can be a significant source of low frequency noise.

Did you make these measurements with the opamp powered up or with V+, V-
open, or even V+ and V- shorted together?