Dr Bruce Griffiths bruce.griffiths@xtra.co.nz wrote:

The jitter from the "phase jerked" 10kHz would be in the several to
tens of ns range, once a second, right?

Period of 10kHz is 1E5 ns.

I don't think I can trust my old analog scopes to do this, but a
fancy coincident trigger (require coincidence with PPS)
on a digital storage scope with a crystal timebase might see this.
Sounds more like a job for histogramming interval measuremnts.
(In my lab days we did this with a TAC followed by a PHA for
much larger scale jitter measurements).

Tim.

Tim Shoppa wrote:

Yes the phase jerks on the 10KHz output should be virtually identical to
the phase jitter on the PPS output.
A digital scope is probably necessary unless one can digitally delay the
PPS signal (without affecting the timing of the 10KHz signal phase jerks
) using the receiver clock that is used to position the PPS pulse.
If the 10KHz output were delayed by 100usec (jitter less than that of
the PPS pulse) and the PPS signal was used to trigger the scope then it
may be possible to use an analog scope together with an oscilloscope
camera to capture the waveform.
Unfortunately this is now probably impractical although a few decades
ago it would have been relatively simple but time consuming.

In principle this measurement could be made with a time interval counter:
PPS -> START
delayed 10KHz -> STOP

Vary the delay and watch the jitter jump when the leading edge of the
PPS signal occurs during the 10KHz burst which was phase coherent with
the previous PPS pulse.
The only problem is finding a suitable variable delay device with
sufficiently low (<=1ns??) jitter.

Time stamping the 10KHz and PPS pulse transitions with adequate
resolution and sufficiently low jitter would probably be the most effective.
The time stamp records can be accumulated for a few minutes and then
analysed in software.

Bruce

Dr Bruce Griffiths said the following on 10/22/2006 07:33 PM:

The few experiments I've done indicate that there isn't that much
sample-to-sample jitter in a divider built up out of a reasonable-length
string of 74HC390 dividers, but the temperature stability is horrible.

John

Dr Bruce Griffiths said the following on 10/22/2006 08:24 PM:

Hi Bruce --

I believe you're correct that the 10kHz output jitter is not any better
than the 1 PPS jitter; there's been some confusion about that in some of
the projects that use the Jupiter receivers.

John

Dr Bruce Griffiths wrote:

I believe the main benefit of using the 10 kHz output is the easier
filtering, and the optional capability of speeding up the loop for the
initial lock, which may only be useful for experimentation (to verify
that the loop does lock), as any loop speed up will degrade the short
term stability.

However, if the 10 kHz is the open loop crystal for .9999 second, then
resynced at 1 Hz, there is no advantage whatsoever, since the main
error/correction component will still be at 1 Hz. That should be easy to
check.

I am not sure what the advantage of the 10 kHz output is, then?

Didier

Dr Bruce Griffiths wrote:

The delay device can be triggered by the 1 PPS, then will drive the ARM
input of the counter, so as long as the delay device's jitter  is less
than the 10 kHz period, if we adjust the delay to 0.99985 second
(between the last 2 periods of 10 kHz before the 1 PPS), then the TI
counter will START on the last 10 kHz pulse before the pps, and STOP on
the 1 PPS.
Tek has some time delay generators in the TM-500 and 7000 plug-in
series. I knew one day I would need one of those, I now know why :-)

Didier

John Ackermann N8UR wrote:

This propagation delay drift may degrade the measurement accuracy of
long term trends in the time difference between the divider PPS output
and another PPS source such as a GPS receiver. Resynchronising the
divider output to the divider clock will drastically reduce this
particuarly if a fast (ACMOS?) D flipflop is used. However using a
ripple counter divider chain means that for a PPS output,
synchronisation to the divider input frequency may require cascaded
synchronisers. First synchronising to a frequency generated by the first
divider stage to ensure that the divider PPS output transitions do
always occur well away from the synchronising clock transitions despite
worst case propagation delay variations. Finally the output of this
synchronisers is itself synchronised to the divider input clock using
another D flipflop.

The temperature dependent variation of the GPS receiver delay and (for
long cable lengths) the antenna cable delay may also be problematic
particularly if high accuracy is required. This is why some geodetic GPS
receiver installations regulate the temperature of the antenna, preamp,
receiver and associated cabling.

Bruce

You can do a lot worse than straight TTL.  Some useful graphs on pages 102
and 103 of Rohde's "Microwave and Wireless Synthesizers: Theory and Design".

Hint: Look it up at www.amazon.com and you can view those two pages, if you
search within the book for the phrase "170 dB".

-- john, KE5FX

John Miles wrote:

I have a copy of this.
However I find that these graphs appear somewhat inconsistent.
Figure 2-15 should be used for comparing the various logic families.
For a valid comparison the input frequencies and output frequencies
should be the same.

When you actually critically examine the data, TTL is nowhere near as
good as implied by the text.
This book is somewhat variable in the quality of its information.
Some of it is very good, some of it is just incorrect.

Bruce

Didier Juges wrote:

You could always use an HP5359A.
These are still available on the surplus market.

However if a jitter of say 100ns is OK you can easily construct a
suitable digital delay device using a 10MHz clock (slower if more jitter
is OK).
Although it could be built using a collection of CMOS parts it may be
much simpler and cleaner to use a programmable gate array or its equivalent.
Loading the required delay via a synchronous serial interface will
reduce the board layout complexity.
It is essential to use a synchroniser (shift register) to synchronise
the input PPS pulse to the delay generator clock to minimise the
probability of metastability induced problems.

Bruce